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ADS62P15IRGCTG4

更新时间： 2024-11-02 04:04:43
品牌 Logo 应用领域
德州仪器 - TI 转换器模数转换器双倍数据速率
页数 文件大小 规格书
57页 1206K
描述
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

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ADS62P15IRGCTG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC64,.35SQ,20针数：64
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
最大模拟输入电压：2 V最小模拟输入电压：
转换器类型：ADC, PROPRIETARY METHODJESD-30 代码：S-PQCC-N64
JESD-609代码：e4长度：9 mm
最大线性误差 (EL)：0.1709%湿度敏感等级：3
模拟输入通道数量：2位数：11
功能数量：1端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式：PARALLEL, WORD
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC64,.35SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：1.8/3.3,3.3 V认证状态：Not Qualified
采样速率：125 MHz采样并保持/跟踪并保持：SAMPLE
座面最大高度：1 mm子类别：Analog to Digital Converters
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：9 mm
Base Number Matches：1

ADS62P15IRGCTG4 数据手册

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ADS62P15  
www.ti.com  
SLAS572–OCTOBER 2007  
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs  
1
FEATURES  
Reference also  
•
•
•
•
•
•
•
Maximum Sample Rate: 125 MSPS  
11-Bit Resolution With No Missing Codes  
84 dBc SFDR at Fin = 50 MHz  
•
•
64-QFN Package (9mm × 9mm)  
Pin Compatible 14-bit and 12-bit Family  
(ADS62P4X/ADS62P2X)  
67.1 dBFS SNR at Fin = 50 MHz  
92 dB Crosstalk  
APPLICATIONS  
•
•
•
•
•
•
•
Wireless Communications Infrastructure  
Software Defined Radio  
Power Amplifier Linearization  
802.16d/e  
Medical Imaging  
Radar Systems  
Parallel CMOS and DDR LVDS Output Options  
3.5 dB Coarse Gain and Programmable Fine  
Gain up to 6 dB for SNR/SFDR Trade-Off  
•
Digital Processing Block With:  
–
–
–
–
Offset Correction  
Fine Gain Correction, in Steps of 0.05 dB  
Decimation by 2/4/8  
Test and Measurement Instrumentation  
Table 1. ADS62PXX Dual Channel Family  
Built-in and Custom Programmable 24-Tap  
Low/High /Band Pass Filters  
125 MSPS  
105 MSPS  
80 MSPS  
65 MSPS  
ADS62P4X  
(14 bit)  
•
Supports Sine, LVPECL, LVDS & LVCMOS  
Clocks & Amplitude Down to 400 mVPP  
ADS62P45  
ADS62P44  
ADS62P43  
ADS62P42  
ADS62P2X  
(12 bit)  
ADS62P25  
ADS62P15  
ADS62P24  
-
ADS62P23  
-
ADS62P22  
-
•
•
Clock Duty Cycle Stabilizer  
(11 bit)  
Internal Reference; Supports External  
DESCRIPTION  
ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high  
performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and  
low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and  
fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.  
ADS62P15 includes a digital processing block that consists of several useful and commonly used digital  
functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and  
in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions  
are disabled.  
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes  
internal references while traditional reference pins and associated decoupling capacitors have been eliminated.  
Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial  
temperature range (–40°C to 85°C).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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