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ADS62P23 PDF预览

ADS62P23

更新时间: 2024-02-27 15:59:08
品牌 Logo 应用领域
德州仪器 - TI 输出元件双倍数据速率
页数 文件大小 规格书
70页 1787K
描述
DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS62P23 技术参数

生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:64
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.5
最大模拟输入电压:2 V最小模拟输入电压:
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-PQCC-N64
JESD-609代码:e4长度:9 mm
模拟输入通道数量:1位数:12
功能数量:2端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态:Not Qualified采样速率:80 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:1 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:9 mm

ADS62P23 数据手册

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ADS62P45, ADS62P44  
ADS62P43, ADS62P42  
www.ti.com  
SLAS561AJULY 2007REVISED FEBRUARY 2008  
DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS  
1
FEATURES  
DESCRIPTION  
Maximum Sample Rate: 125 MSPS  
14-Bit Resolution with No Missing Codes  
95 dB Crosstalk  
ADS62P4X is a dual channel 14-bit A/D converter  
family with maximum sample rates up to 125 MSPS.  
It combines high performance and low power  
consumption in a compact 64 QFN package. Using  
an internal sample and hold and low jitter clock  
buffer, the ADC supports high SNR and high SFDR at  
high input frequencies. It has coarse and fine gain  
options that can be used to improve SFDR  
performance at lower full-scale input ranges.  
Parallel CMOS and DDR LVDS Output Options  
3.5 dB Coarse Gain and Programmable Fine  
Gain up to 6 dB for SNR/SFDR Trade-Off  
Digital Processing Block with:  
Offset Correction  
Fine Gain Correction, in Steps of 0.05 dB  
Decimation by 2/4/8  
ADS62P4X includes a digital processing block that  
consists of several useful and commonly used digital  
functions such as ADC offset correction, fine gain  
correction (in steps of 0.05 dB), decimation by 2,4,8  
and in-built and custom programmable filters. By  
default, the digital processing block is bypassed, and  
its functions are disabled.  
Built-in and Custom Programmable 24-Tap  
Low-/High-/Band-Pass Filters  
Supports Sine, LVPECL, LVDS and LVCMOS  
Clocks and Amplitude Down to 400 mVPP  
Clock Duty Cycle Stabilizer  
Two output interface options exist – parallel CMOS  
and DDR LVDS (Double Data Rate). ADS62P4X  
includes internal references while traditional  
reference pins and associated decoupling capacitors  
have been eliminated. Nevertheless, the device can  
also be driven with an external reference. The device  
is specified over the industrial temperature range  
(–40°C to 85°C).  
Internal Reference; Supports External  
Reference also  
64-QFN Package (9mm × 9mm)  
Pin Compatible 12-Bit Family (ADS62P2X)  
APPLICATIONS  
Wireless Communications Infrastructure  
Software Defined Radio  
Power Amplifier Linearization  
802.16d/e  
Medical Imaging  
Radar Systems  
Test and Measurement Instrumentation  
ADS62P4X Performance Summary  
ADS62P45  
88  
ADS62P44  
ADS62P43  
93  
ADS62P42  
94  
Fin = 10 MHz (0 dB gain)  
Fin = 190 MHz (3.5 dB gain)  
Fin = 10 MHz (0 dB gain)  
Fin = 190 MHz (3.5 dB gain)  
92  
86  
SFDR, dBc  
84  
87  
85  
73.7  
70.8  
799  
74.2  
71  
74.6  
71.3  
594  
74.7  
70.9  
515  
SINAD, dBFS  
Analog Power, mW  
710  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2008, Texas Instruments Incorporated  

ADS62P23 替代型号

型号 品牌 替代类型 描述 数据表
ADS62P24 TI

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DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
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ADS62P15 TI

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