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ADS62P19

更新时间： 2024-01-21 18:54:58
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德州仪器 - TI 双倍数据速率
页数 文件大小 规格书
65页 1550K
描述
Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs

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ADS62P19 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：VQFN-64针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.26最大模拟输入电压：2 V
最小模拟输入电压：-2 V转换器类型：ADC, FLASH METHOD
JESD-30 代码：S-PQCC-N64JESD-609代码：e4
长度：9 mm最大线性误差 (EL)：0.1221%
湿度敏感等级：3模拟输入通道数量：2
位数：11功能数量：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC64,.35SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：1.8,3.3 V
认证状态：Not Qualified采样速率：250 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：1 mm
子类别：Analog to Digital Converters最大压摆率：250 mA
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：9 mmBase Number Matches：1

ADS62P19 数据手册

 浏览型号ADS62P19的Datasheet PDF文件第2页浏览型号ADS62P19的Datasheet PDF文件第3页浏览型号ADS62P19的Datasheet PDF文件第4页浏览型号ADS62P19的Datasheet PDF文件第5页浏览型号ADS62P19的Datasheet PDF文件第6页浏览型号ADS62P19的Datasheet PDF文件第7页 
ADS62P19  
www.ti.com  
SLAS937 –APRIL 2013  
Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs  
Check for Samples: ADS62P19  
1
FEATURES  
DESCRIPTION  
The ADS62P19 is part of a family of dual-channel,  
11-bit, analog-to-digital converters (ADCs) with  
sampling rates up to 250 MSPS. The device  
combines high dynamic performance and low power  
consumption in a compact QFN-64 package. This  
functionality makes the device well-suited for multi-  
carrier, wide-bandwidth communication applications.  
2
•
Maximum Sample Rate: 250 MSPS  
11-Bit Resolution  
•
•
•
Total Power: 1.25 W at 250 MSPS  
Output Options:  
–
DDR LVDS and Parallel CMOS  
Programmable Gain:  
Up to 6 dB for SNR and SFDR Trade-Off  
•
The ADS62P19 has gain options that can be used to  
improve spurious-free dynamic range (SFDR)  
performance at lower full-scale input ranges. The  
device includes a dc offset correction loop that can be  
used to cancel ADC offset. Both double data rate  
(DDR) low-voltage differential signaling (LVDS) and  
parallel complementary metal oxide semiconductor  
(CMOS) digital output interfaces are available.  
–
•
•
•
DC Offset Correction  
Crosstalk: 90 dB  
Supports Input Clock Amplitude Down to  
400 mVPP, Differential  
•
•
Internal and External Reference Support  
Package: 9-mm × 9-mm QFN-64  
Although the device includes internal references, the  
traditional reference pins and associated decoupling  
capacitors are eliminated. Nevertheless, the device  
can also be driven with an external reference. The  
device is specified over the industrial temperature  
range (–40°C to +85°C).  
ADS62Pxx High-Speed Family  
RESOLUTION  
200 MSPS  
210 MSPS  
250 MSPS  
ADS62P19  
ADS62P29  
ADS62P49  
11-bit  
ADS62C17  
—
12-bit  
—
—
ADS62P28  
ADS62P48  
14-bit  
Table 1. Performance Summary  
AT 170-MHz INPUT  
GAIN (dB)  
ADS62P19  
ADS62P28  
78  
ADS62P29  
ADS62P48  
ADS62P49  
0
6
75  
82  
75  
82  
78  
75  
82  
SFDR, dBc  
84  
84  
0
65.3  
64  
68.7  
68.3  
65.8  
1
70.1  
66.3  
0.92  
69.8  
66.5  
1
SINAD, dBFS  
6
65.8  
Analog power, W  
—
1
0.92  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2013, Texas Instruments Incorporated  
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