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ADS58C28IRGC25 PDF预览

ADS58C28IRGC25

更新时间： 2024-11-07 14:48:31
品牌 Logo 应用领域
德州仪器 - TI 接口集成电路
页数 文件大小 规格书
67页 2359K
描述
Dual 11-Bit 200MSPS ADC with SNRBoost 64-VQFN -40 to 85

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ADS58C28IRGC25 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN,针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：8.2
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-PQCC-N64
JESD-609代码：e4长度：9 mm
湿度敏感等级：3功能数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified最大接收延迟：
接收器位数：2座面最大高度：1 mm
最大供电电压：1.9 V最小供电电压：1.7 V
标称供电电压：1.8 V电源电压1-最大：1.9 V
电源电压1-分钟：1.75 V电源电压1-Nom：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：9 mmBase Number Matches：1

ADS58C28IRGC25 数据手册

 浏览型号ADS58C28IRGC25的Datasheet PDF文件第2页浏览型号ADS58C28IRGC25的Datasheet PDF文件第3页浏览型号ADS58C28IRGC25的Datasheet PDF文件第4页浏览型号ADS58C28IRGC25的Datasheet PDF文件第5页浏览型号ADS58C28IRGC25的Datasheet PDF文件第6页浏览型号ADS58C28IRGC25的Datasheet PDF文件第7页 
ADS58C28  
www.ti.com  
SBAS509B –JUNE 2010–REVISED OCTOBER 2010  
Dual Channel IF Receiver with SNRBoost3G  
Check for Samples: ADS58C28  
1
FEATURES  
DESCRIPTION  
23  
•
Maximum Sample Rate: 200MSPS  
The ADS58C28 is  
a
dual-channel, 11-bit  
analog-to-digital converter (ADC) with sampling rates  
up to 200MSPS. The device uses innovative design  
techniques to achieve high dynamic performance,  
while consuming extremely low power at 1.8V supply.  
This architecture makes it well-suited for multi-carrier,  
wide bandwidth communications applications.  
The ADS58C28 uses third-generation SNRBoost3G  
technology to overcome SNR limitation as a result of  
quantization noise (for bandwidths less than Nyquist,  
fS/2). Enhancements in the SNRBoost3G technology  
allow support for SNR improvements over wide  
bandwidths (up to 60MHz). In addition, separate  
SNRBoost3G coefficients can also be programmed for  
each channel.  
•
High Dynamic Performance:  
–
–
83dBc SFDR at 140MHz  
72.5dBFS SNR with 60MHz BW Using  
SNRBoost3G Technology  
•
•
SNRBoost3G Highlights:  
–
–
Supports Wide Bandwidth (up to 60MHz)  
Programmable Bandwidths:  
20MHz, 30MHz, and 40MHz  
–
–
Flat Noise Floor within the Band  
Independent SNRBoost3G Coefficients for  
Both Channels  
Output Interface:  
The device has a digital gain function that can be  
used to improve SFDR performance at lower  
–
Double Data Rate (DDR) LVDS with  
Programmable Swing and Strength:  
full-scale input ranges. It includes  
a dc offset  
–
–
–
–
Standard Swing: 350mV  
correction loop that can be used to cancel the ADC  
offset. The digital outputs of all channels are output  
as double data rate (DDR) low-voltage differential  
signaling (LVDS) together with an LVDS clock output.  
The low data rate of this interface (400MBPS at  
200MSPS sample rate) makes it possible to use  
Low Swing: 200mV  
Default Strength: 100Ω termination  
2x Strength: 50Ω termination  
–
–
Compatible with GC6016  
1.8V Parallel CMOS Interface Also  
Supported  
low-cost  
field-programmable  
gate  
array  
(FPGA)-based receivers. The strength of the LVDS  
output buffers can be increased to support 50Ω  
differential termination. This increase allows the  
output clock signal to be connected to two separate  
receiver chips with an effective 50Ω termination (such  
as the two clock ports of the GC5330). The same  
digital output pins can also be configured as a parallel  
1.8V CMOS interface.  
•
•
Ultralow Power with Single 1.8V Supply:  
–
–
470mW Total Power  
710mW Total Power (200MSPS) with  
SNRBoost3G on Both Channels  
Programmable Gain up to 6dB for  
SNR/SFDR Trade-off  
The device includes internal references while the  
traditional reference pins and associated decoupling  
capacitors have been eliminated. The ADS58C28 is  
specified over the industrial temperature range  
(–40°C to +85°C).  
•
•
•
DC Offset Correction  
Supports Low Input Clock Amplitude  
Package: QFN-64 (9mm × 9mm)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
PowerPAD is a trademark of Texas Instruments Incorporated.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  
1234567...67

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ADS58C28IRGC25 替代型号

型号 品牌 替代类型 描述 数据表
ADS58C28IRGCT TI

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 Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC) 64-VQFN -40 to 85

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