5秒后页面跳转
ADS58C48IPFPR PDF预览

ADS58C48IPFPR

更新时间: 2024-02-02 17:52:49
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路接收机
页数 文件大小 规格书
70页 2375K
描述
Quad Channel IF Receiver with SNRBoost 3G

ADS58C48IPFPR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:HTFQFP,针数:80
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.34Is Samacsys:N
差分输出:YES高电平输入电流最大值:0.00001 A
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-PQFP-G80
JESD-609代码:e4长度:12 mm
湿度敏感等级:3功能数量:4
端子数量:80最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HTFQFP封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:7.5 ns
接收器位数:4座面最大高度:1.2 mm
最大压摆率:330 mA最大供电电压:1.9 V
最小供电电压:1.7 V标称供电电压:1.8 V
电源电压1-最大:1.9 V电源电压1-分钟:1.7 V
电源电压1-Nom:1.8 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:12 mmBase Number Matches:1

ADS58C48IPFPR 数据手册

 浏览型号ADS58C48IPFPR的Datasheet PDF文件第2页浏览型号ADS58C48IPFPR的Datasheet PDF文件第3页浏览型号ADS58C48IPFPR的Datasheet PDF文件第4页浏览型号ADS58C48IPFPR的Datasheet PDF文件第5页浏览型号ADS58C48IPFPR的Datasheet PDF文件第6页浏览型号ADS58C48IPFPR的Datasheet PDF文件第7页 
ADS58C48  
www.ti.com  
SLAS689 MAY 2010  
Quad Channel IF Receiver with SNRBoost 3G  
Check for Samples: ADS58C48  
1
FEATURES  
DESCRIPTION  
Maximum Sample Rate: 200 MSPS  
The ADS58C48 is a quad channel 11-bit A/D  
converter with sampling rate up to 200 MSPS. It uses  
innovative design techniques to achieve high dynamic  
performance, while consuming extremely low power  
at 1.8V supply. This makes it well-suited for  
multi-carrier, wide band-width communications  
applications.  
High Dynamic Performance  
SFDR 82 dBc at 140 MHz  
72.3 dBFS SNR in 60 MHz BW Using  
SNRBoost 3G technology  
SNRBoost 3G Highlights  
3G  
Supports Wide Bandwidth up to 60 MHz  
The ADS58C48 uses third-generation SNRBoost  
technology to overcome SNR limitation due to  
Programmable Bandwidths – 60 MHz, 40  
MHz, 30 MHz, 20 MHz  
quantization noise (for bandwidths < Nyquist, Fs/2).  
3G  
Enhancements in the SNRBoost  
technology allow  
Flat Noise Floor within the Band  
Independent SNRBoost 3G Coefficients for  
support for SNR improvements over wide bandwidths  
3G  
(up to 60 MHz). In addition, separate SNRBoost  
Every Channel  
coefficients can be programmed for each channel.  
Output Interface  
The device has digital gain function that can be used  
to improve SFDR performance at lower full-scale  
input ranges. It includes a dc offset correction loop  
that can be used to cancel the ADC offset.  
Double Data Rate (DDR) LVDS with  
Programmable Swing and Strength  
Standard Swing: 350 mV  
The digital outputs of all channels are output as DDR  
LVDS (Double Data Rate) together with an LVDS  
clock output. The low data rate of this interface (400  
Mbps at 200 MSPS sample rate) makes it possible to  
use low-cost FPGA-based receivers. The strength of  
the LVDS output buffers can be increased to support  
50-Ω differential termination. This allows the output  
clock signal to be connected to two separate receiver  
chips with an effective 50-Ω termination (such as the  
two clock ports of the GC5330).  
Low Swing: 200 mV  
Default Strength: 100-Ω Termination  
2x Strength: 50-Ω Termination  
1.8V Parallel CMOS Interface Also  
Supported  
Ultra-Low Power with Single 1.8-V Supply  
0.9-W Total Power  
1.32-W Total Power (200 MSPS) with  
SNRBoost 3G on all 4 Channels  
The same digital output pins can also be configured  
as a parallel 1.8-V CMOS interface.  
1.12-W Total Power (200 MSPS) with  
SNRBoost 3G on 2 Channels  
It includes internal references while the traditional  
reference pins and associated decoupling capacitors  
have been eliminated. The device is specified over  
the industrial temperature range (–40°C to 85°C).  
Programmable Gain up to 6dB for SNR/SFDR  
Trade-Off  
DC Offset Correction  
Supports Low Input Clock Amplitude  
80-TQFP Package  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  

与ADS58C48IPFPR相关器件

型号 品牌 描述 获取价格 数据表
ADS58H40 TI 四通道 14 位 250MSPS 接收器和反馈 IC

获取价格

ADS58H40IZCR TI Quad-Channel, 250-MSPS Receiver and Feedback ADC

获取价格

ADS58H40IZCRR TI Quad-Channel, 250-MSPS Receiver and Feedback ADC

获取价格

ADS58H43 TI Quad-Channel, 250-MSPS Receiver and Feedback ADC

获取价格

ADS58H43IZCR TI Quad-Channel, 250-MSPS Receiver and Feedback ADC

获取价格

ADS58H43IZCRR TI Quad-Channel, 250-MSPS Receiver and Feedback ADC

获取价格