ADS58C48
www.ti.com
SLAS689 –MAY 2010
Quad Channel IF Receiver with SNRBoost 3G
Check for Samples: ADS58C48
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FEATURES
DESCRIPTION
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Maximum Sample Rate: 200 MSPS
The ADS58C48 is a quad channel 11-bit A/D
converter with sampling rate up to 200 MSPS. It uses
innovative design techniques to achieve high dynamic
performance, while consuming extremely low power
at 1.8V supply. This makes it well-suited for
multi-carrier, wide band-width communications
applications.
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High Dynamic Performance
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SFDR 82 dBc at 140 MHz
72.3 dBFS SNR in 60 MHz BW Using
SNRBoost 3G technology
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SNRBoost 3G Highlights
3G
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Supports Wide Bandwidth up to 60 MHz
The ADS58C48 uses third-generation SNRBoost
technology to overcome SNR limitation due to
Programmable Bandwidths – 60 MHz, 40
MHz, 30 MHz, 20 MHz
quantization noise (for bandwidths < Nyquist, Fs/2).
3G
Enhancements in the SNRBoost
technology allow
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Flat Noise Floor within the Band
Independent SNRBoost 3G Coefficients for
support for SNR improvements over wide bandwidths
3G
(up to 60 MHz). In addition, separate SNRBoost
Every Channel
coefficients can be programmed for each channel.
Output Interface
The device has digital gain function that can be used
to improve SFDR performance at lower full-scale
input ranges. It includes a dc offset correction loop
that can be used to cancel the ADC offset.
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Double Data Rate (DDR) LVDS with
Programmable Swing and Strength
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Standard Swing: 350 mV
The digital outputs of all channels are output as DDR
LVDS (Double Data Rate) together with an LVDS
clock output. The low data rate of this interface (400
Mbps at 200 MSPS sample rate) makes it possible to
use low-cost FPGA-based receivers. The strength of
the LVDS output buffers can be increased to support
50-Ω differential termination. This allows the output
clock signal to be connected to two separate receiver
chips with an effective 50-Ω termination (such as the
two clock ports of the GC5330).
Low Swing: 200 mV
Default Strength: 100-Ω Termination
2x Strength: 50-Ω Termination
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1.8V Parallel CMOS Interface Also
Supported
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Ultra-Low Power with Single 1.8-V Supply
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0.9-W Total Power
1.32-W Total Power (200 MSPS) with
SNRBoost 3G on all 4 Channels
The same digital output pins can also be configured
as a parallel 1.8-V CMOS interface.
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1.12-W Total Power (200 MSPS) with
SNRBoost 3G on 2 Channels
It includes internal references while the traditional
reference pins and associated decoupling capacitors
have been eliminated. The device is specified over
the industrial temperature range (–40°C to 85°C).
Programmable Gain up to 6dB for SNR/SFDR
Trade-Off
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DC Offset Correction
Supports Low Input Clock Amplitude
80-TQFP Package
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
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Copyright © 2010, Texas Instruments Incorporated