Datasheet > ADS58J89IRGCR

ADS58J89IRGCR

更新时间： 2024-01-20 21:11:04

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
77页	2305K
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ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC

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ADS58J89

SBAS659 –NOVEMBER 2014

ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC

1 Features

3 Description

The ADS58J89 is a high-linearity, quad-channel, 14-

bit, 250/500-MSPS IF (intermediate frequency)

receiver. The four channels contain 500MSPS 14-bit

ADCs followed by signal processing for wireless

infrastructure systems. The channels can be

configured in various modes depending on

bandwidth, resolution and sample time requirements.

The signal processing block contains selectable

modes for decimation filters, SNR Boost filters,

resolution versus time and time-division duplex (TDD)

burst mode. Designed for high antenna count

systems, the 4 channels provides high bandwidth and

linearity to multi-channel receivers in a small footprint.

The device can be dual function as traffic receiver

and power amplifier linearization feedback path in

TDD systems.

•

4-Ch, 14-Bit 500MSPS With Digital Signal

Processing

•

Power Amplifier Linearization (Feedback) Modes

–

14-Bits Every Other Sample at 250MSPS

Programmable Resolution vs Duty Cycle

–

Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)

Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)

Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)

•

Traffic Receiver Modes

–

14-Bit 250MSPS: Decimate by 2 Filter,

High/Low Pass

9-Bit SNR-Boost Filter (150-MHz Max

Bandwidth)

Key Specifications:

9-to-14-Bit TDD Burst (200-MHz Max

Bandwidth)

•

Power Dissipation: 875 mW/ch

Input Bandwidth (3dB): 900 MHz

Aperture Jitter: 98 fs rms

Channel Isolation: 85 dB

Performance at ƒ_in= 170 MHz at 1.25 Vpp,

–1 dBFS

•

Flexible Input Clock Buffer With Divide by 1/2/4

JESD204B Digital Interface up to 5.0Gbps

–

1 or 2 Lanes per Channel, With Subclass 1

•

64-Pin VQFN Package (9 × 9 mm)

–

SNR: 65.8 dBFS

SFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3

2 Applications

•

Multi-Carrier, Multi-Mode, Multi-Band Cellular

Receivers

Device Information⁽¹⁾

–

TDD-LTE

PART NUMBER

ADS58J89

PACKAGE

MAX OUTPUT RATE

FDD-LTE

VQFN (64)

500 MSPS

CDMA, WCMDA, CMDA2k

GSM

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

RF and Microwave Backhaul

Simplified Schematic

–

Point-to-Point Backhaul

OVRA

Point-to-Multi-Point Backhaul

2x Dec

14-bit

ADC

Burst Mode

SNR Boost

JESD204B

INAP/M

INBP/M

DA[0,1]P/M

•

Wireless Repeaters

Distributed Antenna Systems (DAS)

Broadband Wireless

2x Dec

Burst Mode

SNR Boost

14-bit

ADC

DB[0,1]P/M

OVRB

SYSREFABP/M

CLKINP/M

SYNCbAB

SYNCbCD

Divide by

1, 2, 4

PLL

x10/x20

SYSREFCDP/M

OVRC

2x Dec

Burst Mode

SNR Boost

14-bit

ADC

JESD204B

DC[0,1]P/M

INCP/M

2x Dec

Burst Mode

SNR Boost

14-bit

ADC

INDP/M

VCM

DD[0,1]P/M

OVRD

Common

Mode

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...77

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与ADS58J89IRGCR相关器件

型号	品牌	获取价格	描述	数据表
ADS58J89IRGCT	TI	获取价格	ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC
ADS602	ETC	获取价格
ADS602JG	BB	获取价格	ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, CDI
ADS602KG	BB	获取价格	ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, CDI
ADS605	ETC	获取价格	12-Bit 10MSPS Analog-to-Digital Converter
ADS605H	BB	获取价格	ADC, Flash Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid, CDIP28,
ADS605HB	BB	获取价格	ADC, Flash Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid, CDIP28,
ADS61	TI	获取价格	Wideband Transmit-Receive Digital Signal Processors
ADS610	ETC	获取价格
ADS610H	BB	获取价格	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid, CDIP40,

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