Integrated Power Solution
with Quad Low Noise Buck Regulators
Data Sheet
ADP5014
FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage range: 2.75 V to 6.0 V
ADP5014
VREF
R
RT
RT
Programmable output voltage range: 0.5 V to 0.9 × PVINx
Low output noise: ~25 μV rms when VOUT ≤ VREF
1.0ꢀ output accuracy over full temperature range
500 kHz to 2.5 MHz adjustable switching frequency
Power regulation
Channel 1 and Channel 2: programmable 2 A/4 A sync
buck regulators, or single 8 A output in parallel
Channel 3 and Channel 4: programmable 1 A/2 A sync
buck regulators, or single 4 A output in parallel
Flexible parallel operation
C1
OSC
REF
EN1/ENALL
EN2/DL12
EN3/UV
CFG1
CFG2
GPIO
LOGIC DECODER
EN4/DL34
AVIN
FB1
2.75V TO 6.0V
PVIN1
SW1
C2
L1
CH 1
LOW-NOISE BUCK
(2A/4A)
VOUT1
C3
PVIN1
VSET1
VREF
PGND1
COMP1
PVIN2
FB2
Precision enable with 0.6 V threshold
Manual or sequence mode for power-up and power-down
sequence
SW2
C4
CH 2
LOW-NOISE BUCK
(2A/4A)
L2
VOUT2
C5
VREF
VSET2
PGND2
Selective FPWM or PSM operation mode
Precision undervoltage comparator
Frequency synchronization input or output
Active output discharge switch
Power-good flag on selective channels via factory fuse
UVLO, OVP, OCP, and TSD protection
COMP2
PVIN3
L3
VOUT3
C7
SW3
FB3
C6
VREF
CH 3
VSET3
LOW-NOISE BUCK
(1A/2A)
PGND3
COMP3
40-lead, 6 mm × 6 mm LFCSP package
−40°C to +125°C junction temperature
PVIN4
L4
VOUT4
C9
SW4
FB4
C8
VREF
CH 4
LOW-NOISE BUCK
(1A/2A)
VSET4
APPLICATIONS
PGND4
COMP4
RF transceiver, high speed analog-to-digital converter
(ADC)/digital-to-analog converter (DAC), mixed signal ASIC
FPGA and processor applications
AGND
EXPOSED PAD
Security and surveillance
Figure 1.
Medical applications
GENERAL DESCRIPTION
The ADP5014 combines four high performance, low noise
buck regulators in a 40-lead LFCSP package. Relying on its low
output noise (~25 μV rms when VOUT ≤ VREF), the low noise
buck regulator enables the powering up of the noise sensitive
signal chain products.
The ADP5014 features two enable modes. The manual mode
has four individual precision enable pins to enable each
regulator manually. Alternatively, the sequence mode has one
grouped precision enable signal with programmable power-up
and power-down delay timers on each rail for specific rail
sequence requirements.
All channels in the ADP5014 integrate high-side and low-side
power metal-oxide semiconductor field effect transistors
(MOSFET). Channel 1 and Channel 2 deliver a programmable
output current of 2 A or 4 A. Combining Channel 1 and
Channel 2 in a parallel configuration provides a single output
with up to 8 A of current.
The switching frequency of the ADP5014 can be programmed
or synchronized to an external clock from 500 kHz to 2.5 MHz.
The ADP5014 offers other key features like selective forced
pulse width modulation (FPWM)/power saving mode (PSM),
an undervoltage output (UVO), active output discharge, and a
power-good flag. Other safety features include input under-
voltage lockout (UVLO), overvoltage protection (OVP),
overcurrent protection (OCP) and thermal shutdown (TSD).
Channel 3 and Channel 4 deliver a programmable output current
of 1 A or 2 A. Combining Channel 3 and Channel 4 in a parallel
configuration can provide a single output with up to 4 A of
current.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
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Tel: 781.329.4700 ©2017–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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