Datasheet > ADP5003CP-EVALZ

ADP5003CP-EVALZ

更新时间： 2024-11-27 02:52:23

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
31页	1013K
描述
Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO

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ADP5003CP-EVALZ 数据手册

Low Noise Micro PMU,

3 A Buck Regulator with 3 A LDO

ADP5003

Data Sheet

FEATURES

Low noise, dc power supply system

FUNCTIONAL BLOCK DIAGRAM

PVIN1

4.2V TO 15V

PVIN1

High efficiency buck for first stage conversion

High PSRR, low noise LDO regulator to remove switching

ripple

Adaptive LDO regulator headroom control option for

optimal efficiency and PSRR across full load range

3 A, low noise, buck regulator

EN1

PVIN1

VOUT1

SW1

COMP1

PVOUT1

BUCK

REGULATOR

0.6V TO 5.0V

PVOUT1

BOT1

VSET1

PGND1

TOP1

Wide input voltage range: 4.2 V to 15 V

Programmable output voltage range: 0.6 V to 5.0 V

0.3 MHz to 2.5 MHz internal oscillator

VREG

PVINSYS

4.2V TO 15V

PVINSYS

PWRGD

SYSTEM

0.3 MHz to 2.5 MHz SYNC frequency range

3 A, low noise, NFET LDO regulator (active filter)

Wide input voltage range: 0.65 V to 5 V

Programmable output voltage range: 0.6 V to 3.3 V

Differential point of load remote sensing

3 µV rms output noise (independent of output voltage)

PSRR > 50 dB (to 100 kHz) with 400 mV headroom at 3 A

Ultrafast transient response

PVINSYS

SYNC

REFOUT

PVIN2

VSET2

VBUF

PVOUT2

0.6V TO 3.3V

LOW NOISE

LDO ACTIVE

FILTER

VBUF

Power-good output

VREG_LDO

PVOUT2

LOAD

Precision enable inputs for both the buck regulator and LDO

−40°C to +125°C operating junction temperature range

32-lead, 5 mm × 5 mm, LFCSP

VREG_LDO

VFB2P

VFB2N

EN2

AGND1

AGND2

APPLICATIONS

Low noise power for high speed analog-to-digital converter

(ADC) and digital-to-analog converter (DAC) designs

Powering RF transceivers and clocking ICs

Figure 1.

GENERAL DESCRIPTION

The ADP5003 integrates a high voltage buck regulator and an

ultralow noise low dropout (LDO) regulator in a small, 5 mm ×

5 mm, 32-lead LFCSP package to provide highly efficient and

quiet regulated supplies.

programmed using resistor dividers.

The LDO regulator output can be accurately controlled at the

point of load (POL) using remote sensing that compensates for the

printed circuit board (PCB) trace impedance while delivering

high output currents.

The buck regulator is optimized to operate at high output

currents up to 3 A. The LDO is capable of a maximum output

current of 3 A and operates efficiently with low headroom

voltage while maintaining high power supply rejection.

Each regulator is activated via a dedicated precision enable

input. The buck switching frequency can be synchronized to

an external signal, or programmed with an external resistor.

The ADP5003 can operate in one of two modes. Adaptive mode

allows the LDO to operate with an optimized headroom by

adjusting the buck output voltage internally in response to the

LDO load current. Alternatively, the ADP5003 can operate in

independent mode, where both regulators operate separately

from each other, and where the output voltages are

Safety features in the ADP5003 include thermal shutdown (TSD),

input undervoltage lockout (UVLO) and independent current

limits for each regulator. The ADP5003 is rated for a −40°C to

+125°C operating junction temperature range.

Rev. A

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed byAnalog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksare the property oftheir respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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