6-Bit Programmable 2- to 4-Phase
Synchronous Buck Controller
ADP3196
FUNCTIONAL BLOCK DIAGRAM
FEATURES
VCC
31
RT
12
RAMPADJ
13
Selectable 2-, 3-, or 4-phase operation at up to 1 MHz
per phase
SHUNT
REGULATOR
10 ꢀV worst-case differential sensing error over
teꢀperature
Logic-level PWM outputs for interface to external
high power drivers
Enhanced PWM flex ꢀode for excellent load transient
perforꢀance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
19
OSCILLATOR
OD
UVLO
SHUTDOWN
SET EN
RESET
+
18
1
GND
EN
30
29
CMP
PWM1
PWM2
–
+
–
+
800mV
CSREF
CMP
RESET
–
+
CURRENT
BALANCING
CIRCUIT
CMP
RESET
28
27
PWM3
PWM4
–
+
1.8V
–
2-/3-/4-PHASE
DRIVER LOGIC
+
+
–
CMP
RESET
–
DAC – 250mV
CURRENT
LIMIT
Digitally prograꢀꢀable 0.3750 V to 1.55 V output
Prograꢀꢀable short-circuit protection with prograꢀꢀable
latch-off delay
2
DELAY
PWRGD
CROWBAR
25
24
SW1
SW2
SW3
SW4
TTSENSE 10
THERMAL
THROTTLING
CONTROL
23
22
9
VRMHOT
APPLICATIONS
8
VRM_OFF
Desktop PC power supplies for next generation
AMD processors
VRM ꢀodules
17 CSCOMP
11
7
ILIMIT
CURRENT
MEASUREMENT
AND LIMIT
15
+
–
CSREF
DELAY
16
CSSUM
GENERAL DESCRIPTION
21 IMON
IREF 20
The ADP31961 is a highly efficient multiphase synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Advanced Micro Devices, Inc. (AMD) processors.
It uses an internal 6-bit DAC to read a voltage identification
(VID) code directly from the processor, which is used to set the
output voltage between 0.3750 V and 1.55 V.
–
+
4
FB
5
COMP
+
PRECISION
REFERENCE
14
LLSET
–
FBRTN
3
SOFT START
CONTROL
6
SS
VID DAC
37
ADP3196
34
35
36
38
39
This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase
relationship of the output signals can be programmed to provide
2-, 3-, or 4-phase operation, allowing for the construction of up to
four complementary buck switching stages.
VID5 VID4 VID3 VID2 VID1 VID0
Figure 1. Functional Block Diagram
The ADP3196 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power-
good output that accommodates on-the-fly output voltage
changes requested by the CPU. The ADP3196 has a built-in
shunt regulator that allows the part to be connected to the 12 V
system supply through a series resistor.
The ADP3196 supports a programmable slope function to
adjust the output voltage as a function of the load current so
that it is always optimally positioned for a system transient.
This can be disabled by connecting Pin LLSET to Pin CSREF.
The ADP3196 is specified over the extended commercial
temperature range of 0°C to +85°C and is available in a
40-lead LFCSP.
1Protected by U.S. Patent Number 6,683,441; others patents pending.
©2008 SCILLC. All rights reserved.
January 2008 – Rev. 1
Publication Order Number:
ADP3196/D