Datasheet > ADN2807ACP

ADN2807ACP

更新时间： 2024-02-21 07:57:50

品牌	Logo	应用领域
亚德诺 - ADI		放大器时钟
页数	文件大小	规格书
20页	354K
描述
155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

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ADN2807ACP 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	LFCSP-48	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	5A991.B.3
HTS代码：	8542.39.00.01	风险等级：	5.28
应用程序：	SONET;SDH	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC48,.27SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.215 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	BIPOLAR	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm

ADN2807ACP 数据手册

ADN2807

NIN

QUANTIZER

CDR

RETIMED

50Ω 50Ω

FROM

QUANTIZER

OUTPUT

DATA

CLK

VREF

50Ω 50Ω

VCC

TDINP/N

LOOPEN BYPASS DATAOUTP/N

CLKOUTP/N SQUELCH

Figure 19. Test Modes

The loopback mode can be invoked by driving the LOOPEN

pin to a TTL high state, which facilitates system diagnostic

testing. This will connect the test inputs (TDINP/N) to the

clock and data recovery circuit (per Figure 19). The test inputs

have internal 50 Ω terminations and can be left floating when

not in use. TDINP/N are CML inputs and can be dc-coupled

only when being driven by CML outputs. The TDINP/N inputs

must be ac-coupled if driven by anything other than CML

outputs. Bypass and loop-back modes are mutually exclusive;

only one of these modes can be used at any given time. The

ADN2807 is put into an indeterminate state if both BYPASS

and LOOPEN pins are set to Logic 1 at the same time.

SQUELCH MODE

When the squelch input is driven to a TTL high state, both the

clock and data outputs are set to the zero state to suppress

downstream processing. If desired, this pin can be directly

driven by the LOS (loss-of-signal) detector output (SDOUT). If

the squelch function is not required, the pin should be tied to

VEE.

TEST MODES—BYPASS AND LOOP-BACK

When the bypass input is driven to a TTL high state, the

quantizer output is connected directly to the buffers driving the

data out pins, thus bypassing the clock recovery circuit

(Figure 19). This feature can help the system to deal with

nonstandard bit rates.

Rev. A | Page 14 of 20

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与ADN2807ACP相关器件

型号	品牌	获取价格	描述	数据表
ADN2807ACP-RL	ADI	获取价格	155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2809	ADI	获取价格	Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
ADN2809XCP	ADI	获取价格	Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
ADN2809XCP-RL	ADI	获取价格	Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
ADN2811	ADI	获取价格	OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
ADN2811ACP-CML	ADI	获取价格	OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
ADN2811ACP-CML-RL	ADI	获取价格	OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
ADN2812	ADI	获取价格	Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting
ADN2812ACP	ADI	获取价格	Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting
ADN2812ACP-RL	ADI	获取价格	Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting

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