ADN2809

更新时间： 2024-02-27 15:40:56

品牌	Logo	应用领域
亚德诺 - ADI		放大器时钟
页数	文件大小	规格书
13页	183K
描述
Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier

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ADN2809 数据手册

Multi-Rate to 2.7Gbps Clock and Data

Recovery IC with Limiting Amplifier

Preliminary Technical Data

ADN2809

FEATURES

Meets SONET Requirements for Jitter Transfer /

Generation / Tolerance

Quantizer Sensitivity: 6 mV typical

PRODUCT DESCRIPTION

The ADN2809 provides the receiver functions of Quantization,

Signal Level Detect and Clock and Data Recovery at rates of

OC-3, OC-12, Gigabit Ethernet, OC-48 and all FEC rates. All

SONET jitter requirements are met, including: Jitter Transfer;

Jitter Generation; and Jitter Tolerance. All specifications are

quoted for -40 to 85C ambient temperature unless otherwise

noted.

Adjustable Slice Level: +/- 100 mV

1.9GHz minimum Bandwidth

Loss of Signal Detect Range: 4mV to 17mV

Single Reference Clock Frequency for all rates

Including 15/14 (7%) Wrapper Rate

The device is intended for WDM system applications and can be

used with either an external reference clock or an on-chip

oscillator crystal. Both native rates and 15/14 rate digital

‘wrappers’ rates are supported by the ADN2809, without any

change of reference clock required.

Choice of 19.44, 38.88, 77.76 or

155.52MHz

LVPECL / LVDS / LVCMOS / LVTTL compatible

inputs (LVPECL / LVDS only at 155.52 MHz)

19.44MHz Crystal Oscillator for Module apps

Loss of Lock indicator

Loopback mode for High Speed Test Data

Output Squelch & Clock Recovery Functions

Single Supply Operation: 3.3 Volts (+10%)

Low Power: 780 mW Typical

This device together with a PIN diode and a TIA preamplifier

can implement a highly integrated, low cost, low power fiber

optic receiver.

The receiver front end Signal Detect circuit indicates when the

input signal level has fallen below a user adjustable threshold.

Patented Clock Recovery Architecture

7 x 7 mm 48 pin LFCSP

The ADN2809 is available in a compact 48 pin chip scale

package.

APPLICATIONS

SONET OC-3/12/48, SDH STM-1/4/16, and all

associated FEC rates

WDM transponders

SONET/SDH regenerators and test equipment

Backplane applications

Loss of lock

Functional Block Diagram

REV. PrB Sept 2001

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

©Analog Devices, Inc., 2001

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