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ADN2811ACP-CML

更新时间: 2024-10-27 22:05:19
品牌 Logo 应用领域
亚德诺 - ADI 放大器时钟
页数 文件大小 规格书
16页 347K
描述
OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

ADN2811ACP-CML 数据手册

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a OC-48/OC-48 FEC Clock and Data Recovery IC  
with Integrated Limiting Amp  
ADN2811  
FEATURES  
PRODUCT DESCRIPTION  
Meets SONET Requirements for Jitter Transfer/  
Generation/Tolerance  
Quantizer Sensitivity: 4 mV Typ  
Adjustable Slice Level: 100 mV  
1.9 GHz Minimum Bandwidth  
Patented Clock Recovery Architecture  
Loss of Signal Detect Range: 3 mV to 15 mV  
Single Reference Clock Frequency for Both Native  
SONET and 15/14 (7%) Wrapper Rate  
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz  
REFCLK LVPECL/LVDS/LVCMOS/LVTTL  
Compatible Inputs (LVPECL/LVDS Only at 155.52 MHz)  
19.44 MHz Oscillator On-Chip to Be Used with  
External Crystal  
The ADN2811 provides the receiver functions of quantization,  
signal level detect, and clock and data recovery at OC-48 and  
OC-48 FEC rates. All SONET jitter requirements are met,  
including jitter transfer, jitter generation, and jitter tolerance.  
All specifications are quoted for –40C to +85C ambient  
temperature, unless otherwise noted.  
The device is intended for WDM system applications and can  
be used with either an external reference clock or an on-chip  
oscillator with external crystal. Both the 2.48 Gb/s and 2.66 Gb/s  
digital wrapper rate is supported by the ADN2811, without any  
change of reference clock.  
This device, together with a PIN diode and a TIA preamplifier,  
can implement a highly integrated, low cost, low power, fiber  
optic receiver.  
Loss of Lock Indicator  
Loopback Mode for High Speed Test Data  
Output Squelch and Bypass Features  
Single-Supply Operation: 3.3 V  
Low Power: 540 mW Typical  
7 mm 7 mm 48-Lead LFCSP  
The receiver front end signal detect circuit indicates when the  
input signal level has fallen below a user-adjustable threshold.  
The signal detect circuit has hysteresis to prevent chatter at  
the output.  
The ADN2811 is available in a compact 7 mm × 7 mm 48-lead  
chip scale package.  
APPLICATIONS  
SONET OC-48, SDH STM-16, and 15/14 FEC  
WDM Transponders  
Regenerators/Repeaters  
Test Equipment  
Backplane Applications  
FUNCTIONAL BLOCK DIAGRAM  
SLICEP/N  
2
VCC  
VEE  
LOL  
CF1  
CF2  
ADN2811  
LOOP  
FILTER  
2
REFSEL[0..1]  
PIN  
NIN  
2
REFCLKP/N  
XO1  
/n  
FREQUENCY  
LOCK  
DETECTOR  
PHASE  
SHIFTER  
LOOP  
FILTER  
PHASE  
DET.  
QUANTIZER  
VCO  
XTAL  
OSC  
XO2  
FRACTIONAL  
DIVIDER  
VREF  
REFSEL  
LEVEL  
DETECT  
DATA  
RETIMING  
2
2
THRADJ  
SDOUT  
DATAOUTP/N  
CLKOUTP/N  
RATE  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2002 Analog Devices, Inc. All rights reserved.  

ADN2811ACP-CML 替代型号

型号 品牌 替代类型 描述 数据表
ADN2811ACP-CML-RL ADI

完全替代

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

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