Continuous Rate 12.3Mb/s to 2.7Gb/s
Clock and Data Recovery ICs
Preliminary Technical Data
ADN2817/ADN2818
FEATURES
PRODUCT DESCRIPTION
Serial data input: 12.3 Mb/s to 2.7 Gb/s
Exceeds ITU-T Jitter Specifications
The ADN2817/ADN2818 provides the receiver functions of
quantization, signal level detect, and clock and data recovery for
continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The
ADN2817/ADN2818 automatically locks to all data rates
without the need for an external reference clock or
programming. All SONET jitter requirements are exceeded,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
Integrated Limiting Amp: 6mV sensitivity (ADN2817 only)
Adjustable slice level: 100 mV (ADN2817 only)
Patented dual-loop clock recovery architecture
Programmable LOS detect (ADN2817 only)
Slice level and sample phase adjustments (ADN2817 only)
Integrated PRBS Generator and Detector
No reference clock required
Loss of lock indicator
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
Supports Double Data Rate
Relative Bit Error Rate Monitor
Rate Selectivity without the use of a reference clock
I2C™ interface to access optional features
Single-supply operation: 3.3 V
Low power: 650/600 mW (ADN2817/ADN2818)
5 mm × 5 mm 32-lead LFCSP
The ADN2817/ADN2818 have many optional features available
via an I2C interface, e.g. the user can read back the data rate that
the ADN2817/ADN2818 is locked on to, or the user can set the
device to only lock to one particular data rate if provisioning of
data rates is required.
APPLICATIONS
SONET OC-1/3/12/48 and all associated FEC rates
Fibre Channel, 2× Fibre Channel , GbE, HDTV, etc.
WDM transponders
The ADN2817/ADN2818 is available in a compact 5 mm × 5
mm 32-lead chip scale package.
Regenerators/repeaters
Test equipment
FUNCTIONAL
BLOCK DIAGRAM
REFCLKP/N
(optional)
VCC
VEE
LOL
CF1
CF2
Freq/
Lock
Det
Loop
Filter
Slice Adjust
(ADN2817
SLICEP/N
only)
PIN
Phase
Det.
Phase
Shifter
Loop
Filter
VCO
Σ
NIN
VREF
LOS Detect
(ADN2817
only)
Data
Re-Timing
2
I C
Registers
THRADJ SDOUT DATAOUTP/N
CLKOUTP/N
SCK SDA
Figure 1 ADN2817/ADN2818 Functional Block Diagram
Rev.PrA
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