Datasheet > ADN2807ACP

ADN2807ACP

更新时间： 2024-01-18 16:49:15

品牌	Logo	应用领域
亚德诺 - ADI		放大器时钟
页数	文件大小	规格书
20页	354K
描述
155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

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ADN2807ACP 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	LFCSP-48	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	5A991.B.3
HTS代码：	8542.39.00.01	风险等级：	5.28
应用程序：	SONET;SDH	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC48,.27SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.215 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	BIPOLAR	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm

ADN2807ACP 数据手册

ADN2807

APPLICATION INFORMATION

PCB DESIGN GUIDELINES

matched in length and that the CLKOUTP/N and

DATAOUTP/N traces are matched in length. All high speed

CML outputs, CLKOUTP/N and DATAOUTP/N, also require

100 Ω back termination chip resistors connected between the

output pin and VCC. These resistors should be placed as close

as possible to the output pins. These 100 Ω resistors are in

parallel with on-chip 100 Ω termination resistors to create a

50 Ω back termination (Figure 21).

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane to both analog and

digital grounds is recommended. The VEE pins should be

soldered directly to the ground plane to reduce series

inductance. If the ground plane is an internal plane and

connections to the ground plane are made through vias,

multiple vias may be used in parallel to reduce the series

inductance, especially on Pins 33 and 34, which are the ground

returns for the output buffers.

The high speed inputs, PIN and NIN, are internally terminated

with 50 Ω to an internal reference voltage (Figure 22). A 0.1 µF

capacitor is recommended between VREF (Pin 4) and GND to

provide an ac ground for the inputs.

As with any high speed mixed-signal design, care should be

taken to keep all high speed digital traces away from sensitive

analog nodes.

Use of a 10 µF electrolytic capacitor between VCC and GND is

recommended at the location where the 3.3 V supply enters the

PCB. Use of 0.1 µF and 1 nF ceramic chip capacitors should be

placed between IC power supply VCC and GND as close as

possible to the ADN2807’s VCC pins. Again, if connections to

the supply and ground are made through vias, the use of

multiple vias in parallel will help to reduce series inductance,

especially on Pins 35 and 36, which supply power to the high

speed CLKOUTP/N and DATAOUTP/N output buffers. Refer

to the schematic in Figure 20 for recommended connections.

Soldering Guidelines for Chip Scale Package

The leads on the 48-lead LFCSP are rectangular. The printed

circuit board pad for these should be 0.1 mm longer than the

package lead length and 0.05 mm wider than the package lead

width. The land should be centered on the pad. This ensures

that solder joint size is maximized. The bottom of the LFCSP

has a central exposed pad. The pad on the printed circuit board

should be at least as large as this exposed pad. The user must

connect the exposed pad to analog VCC. If vias are used, they

should be incorporated into the pad at 1.2 mm pitch grid. The

via diameter should be between 0.3 mm and 0.33 mm, and the

via barrel should be plated with 1 oz. copper to plug the via.

Transmission Lines

Use of 50 Ω transmission lines are required for all high

frequency input and output signals to minimize reflections,

including PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and

DATAOUTN (also REFCLKP/N for a 155.52 MHz REFCLK). It

is also recommended that the PIN/NIN input traces are

Rev. A | Page 15 of 20

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ADN2807ACP-RL	ADI	155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp	获取价格
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