Datasheet > ADF4360-2_12

ADF4360-2_12

更新时间： 2022-04-13 01:03:50

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	589K
描述
Integrated Synthesizer and VCO

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数据手册

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ADF4360-2_12 数据手册

Data Sheet

ADF4360-2

TIMING CHARACTERISTICS¹

AV_DD= DV_DD= V_VCO= 3.3 V 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T_A= T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

Limit at T_MINto T_MAX(B Version)

Unit

Test Conditions/Comments

LE Setup Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

ns min

DATA to CLOCK Setup Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Setup Time

LE Pulse Width

¹See the Power-Up section for the recommended power-up procedure for this device.

t₄

t₅

CLOCK

t₂

t₃

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB23 (MSB)

DB22

DB2

DATA

t₇

t₁

t₆

Figure 2. Timing Diagram

Rev. C | Page 5 of 24

1 2 3 456 7 8...24

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