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ADF4002SRUZ-EP PDF预览

ADF4002SRUZ-EP

更新时间: 2024-11-20 20:02:35
品牌 Logo 应用领域
亚德诺 - ADI 信息通信管理光电二极管
页数 文件大小 规格书
8页 219K
描述
Phase Detector / PLL Frequency Synthesizer

ADF4002SRUZ-EP 数据手册

 浏览型号ADF4002SRUZ-EP的Datasheet PDF文件第2页浏览型号ADF4002SRUZ-EP的Datasheet PDF文件第3页浏览型号ADF4002SRUZ-EP的Datasheet PDF文件第4页浏览型号ADF4002SRUZ-EP的Datasheet PDF文件第5页浏览型号ADF4002SRUZ-EP的Datasheet PDF文件第6页浏览型号ADF4002SRUZ-EP的Datasheet PDF文件第7页 
Phase Detector/Frequency Synthesizer  
ADF4002-EP  
FEATURES  
GENERAL DESCRIPTION  
400 MHz bandwidth  
2.7 V to 3.3 V power supply  
Separate charge pump supply (VP) allows extended  
tuning voltage in 3 V systems  
Programmable charge pump currents  
3-wire serial interface  
Analog and digital lock detect  
Hardware and software power-down mode  
104 MHz phase frequency detector  
Supports defense and aerospace applications  
(AQEC standard)  
The ADF4002-EP frequency synthesizer is used to implement  
local oscillators in the upconversion and downconversion sections  
of wireless receivers and transmitters. It consists of a low noise  
digital phase frequency detector (PFD), a precision charge pump,  
a programmable reference divider, and a programmable N divider.  
The 14-bit reference counter (R counter) allows selectable REFIN  
frequencies at the PFD input. A complete phase-locked loop (PLL)  
can be implemented if the synthesizer is used with an external  
loop filter and voltage controlled oscillator (VCO). In addition,  
by programming R and N to 1, the part can be used as a stand-  
alone PFD and charge pump.  
Military temperature range: −55°C to +125°C  
Controlled manufacturing baseline  
One assembly/test site  
Additional application and technical information can be found  
in the ADF4002 data sheet.  
One fabrication site  
Enhanced product change notification  
Qualification data available on request  
APPLICATIONS  
Clock conditioning  
Clock generation  
IF LO generation  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DV  
R
SET  
V
CPGND  
DD  
DD  
P
REFERENCE  
14-BIT  
R COUNTER  
PHASE  
FREQUENCY  
DETECTOR  
REF  
CHARGE  
PUMP  
IN  
CP  
14  
R COUNTER  
LATCH  
LOCK  
DETECT  
CURRENT  
SETTING 2  
CURRENT  
SETTING 1  
CLK  
DATA  
LE  
24-BIT INPUT  
REGISTER  
FUNCTION  
LATCH  
CPI6 CPI5 CPI4  
HIGH-Z  
CPI3 CPI2 CPI1  
22  
N COUNTER  
LATCH  
SD  
OUT  
AV  
DD  
MUXOUT  
MUX  
SD  
OUT  
RF  
RF  
A
B
13-BIT  
N COUNTER  
IN  
IN  
M3 M2 M1  
ADF4002-EP  
CE  
AGND DGND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 

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