PLL Frequency Synthesizer
ADF4106
FEATURES
GENERAL DESCRIPTION
6.0 GHz Bandwidth
2.7 V to 3.3 V Power Supply
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital PFD (phase frequency detector), a precision charge pump,
a programmable reference divider, programmable A and B
counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit)
and B (13-bit) counters, in conjunction with the dual-modulus
prescaler (P/P + 1), implement an N divider (N = BP + A). In
addition, the 14-bit reference counter (R counter) allows selectable
REFIN frequencies at the PFD input. A complete PLL (phase-
locked loop) can be implemented if the synthesizer is used with
an external loop filter and VCO (voltage controlled oscillator).
Its very high bandwidth means that frequency doublers can be
eliminated in many high frequency systems, simplifying system
architecture and lowering cost.
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual-Modulus Prescaler
8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
Programmable Antibacklash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Modes
APPLICATIONS
Broadband Wireless Access
Instrumentation
Wireless LANs
Base Stations for Wireless Radio
FUNCTIONAL BLOCK DIAGRAM
AV
V
P
DV
DD
CPGND
R
SET
DD
REFERENCE
14-BIT
R COUNTER
REF
IN
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
14
R COUNTER
LATCH
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CLK
DATA
LE
24-BIT INPUT
REGISTER
FUNCTION
LATCH
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
HIGH Z
22
AB COUNTER
LATCH
FROM
FUNCTION
LATCH
19
AV
DD
MUXOUT
MUX
13
SD
OUT
N = BP + A
13-BIT
B COUNTER
LOAD
M3 M2 M1
RF
A
B
IN
PRESCALER
P/P + 1
RF
IN
LOAD
6-BIT
A COUNTER
ADF4106
6
CE
AGND DGND
REV. A
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