Datasheet > ADF4106-SCPZ-EP-R7

ADF4106-SCPZ-EP-R7

更新时间： 2024-11-09 19:57:07

品牌	Logo	应用领域
亚德诺 - ADI		信息通信管理
页数	文件大小	规格书
12页	315K
描述
PLL FREQUENCY SYNTHESIZER, 6000MHz, QCC16, 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD1, LFCSP-16

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PLL Frequency Synthesizer

ADF4106-EP

FEATURES

GENERAL DESCRIPTION

6.0 GHz bandwidth

2.7 V to 3.3 V power supply

Separate charge pump supply (V_P) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

The ADF4106-EP frequency synthesizer can be used to

implement local oscillators in the up-conversion and down-

conversion sections of wireless receivers and transmitters. It

consists of a low noise, digital phase frequency detector (PFD),

a precision charge pump, a programmable reference divider,

programmable A counter and B counter, and a dual-modulus

prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in

conjunction with the dual-modulus prescaler (P/P + 1), implement

an N divider (N = BP + A). In addition, the 14-bit reference

counter (R counter) allows selectable REF_INfrequencies at the

PFD input. A complete phase-locked loop (PLL) can be

implemented if the synthesizer is used with an external loop

filter and voltage controlled oscillator (VCO). Its very high

bandwidth means that frequency doublers can be eliminated in

many high frequency systems, simplifying system architecture

and reducing cost.

Support defense and aerospace applications (AQEC)

Military temperature range (−55°C to +125°C)

Controlled manufacturing baseline

One assembly/test site

One fabrication site

Enhanced product change notification

Qualification data available upon request

Additional application and technical information can be found

in the ADF4106 data sheet.

APPLICATIONS

Broadband wireless access

Satellite systems

Instrumentation

Wireless LANS

Base stations for wireless radios

FUNCTIONAL BLOCK DIAGRAM

SET

CPGND

REFERENCE

14-BIT

R COUNTER

PHASE

FREQUENCY

DETECTOR

REF

CHARGE

PUMP

R COUNTER

LATCH

LOCK

DETECT

CURRENT

SETTING 2

CURRENT

SETTING 1

CLK

DATA

24-BIT INPUT

FUNCTION

LATCH

CPI6 CPI5 CPI4

HIGH Z

CPI3 CPI2 CPI1

A, B COUNTER

LATCH

FROM

OUT

FUNCTION

LATCH

MUXOUT

MUX

13-BIT

N = BP + A

OUT

B COUNTER

LOAD

PRESCALER

P/P + 1

LOAD

M3 M2 M1

6-BIT

A COUNTER

ADF4106-EP

AGND DGND

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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