ADF4106BRUZ-RL

更新时间： 2024-01-02 12:58:16

品牌	Logo	应用领域
亚德诺 - ADI		信号电路锁相环或频率合成电路光电二极管 PC
页数	文件大小	规格书
24页	361K
描述
PLL Frequency Synthesizer

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ADF4106BRUZ-RL 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.65
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	Base Number Matches：	1

ADF4106BRUZ-RL 数据手册

PLL Frequency Synthesizer

Data Sheet

ADF4106

FEATURES

GENERAL DESCRIPTION

6.0 GHz bandwidth

2.7 V to 3.3 V power supply

Separate charge pump supply (V_P) allows extended

tuning voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

The ADF4106 frequency synthesizer can be used to implement

local oscillators in the up-conversion and down-conversion

sections of wireless receivers and transmitters. It consists of a

low noise, digital phase frequency detector (PFD), a precision

charge pump, a programmable reference divider, programmable

A counter and B counter, and a dual-modulus prescaler (P/P + 1).

The A (6-bit) counter and B (13-bit) counter, in conjunction

with the dual-modulus prescaler (P/P + 1), implement an N

divider (N = BP + A). In addition, the 14-bit reference counter

(R Counter) allows selectable REF_INfrequencies at the PFD

input. A complete phase-locked loop (PLL) can be implemented

if the synthesizer is used with an external loop filter and voltage

controlled oscillator (VCO). Its very high bandwidth means

that frequency doublers can be eliminated in many high

frequency systems, simplifying system architecture and

reducing cost.

APPLICATIONS

Broadband wireless access

Satellite systems

Instrumentation

Wireless LANS

Base stations for wireless radios

FUNCTIONAL BLOCK DIAGRAM

SET

CPGND

REFERENCE

14-BIT

R COUNTER

PHASE

FREQUENCY

DETECTOR

REF

CHARGE

PUMP

R COUNTER

LATCH

LOCK

DETECT

CURRENT

SETTING 2

CURRENT

SETTING 1

CLK

DATA

24-BIT INPUT

FUNCTION

LATCH

CPI6 CPI5 CPI4

HIGH Z

CPI3 CPI2 CPI1

A, B COUNTER

LATCH

FROM

OUT

FUNCTION

LATCH

MUXOUT

MUX

13-BIT

N = BP + A

OUT

B COUNTER

LOAD

PRESCALER

P/P + 1

LOAD

M3 M2 M1

6-BIT

A COUNTER

ADF4106

AGND

DGND

Figure 1.

Rev. E

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

12 3 4 5 6 7...24

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