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ADF4106BCPZ

更新时间: 2024-11-24 12:29:07
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 361K
描述
PLL Frequency Synthesizer

ADF4106BCPZ 数据手册

 浏览型号ADF4106BCPZ的Datasheet PDF文件第2页浏览型号ADF4106BCPZ的Datasheet PDF文件第3页浏览型号ADF4106BCPZ的Datasheet PDF文件第4页浏览型号ADF4106BCPZ的Datasheet PDF文件第5页浏览型号ADF4106BCPZ的Datasheet PDF文件第6页浏览型号ADF4106BCPZ的Datasheet PDF文件第7页 
PLL Frequency Synthesizer  
Data Sheet  
ADF4106  
FEATURES  
GENERAL DESCRIPTION  
6.0 GHz bandwidth  
2.7 V to 3.3 V power supply  
Separate charge pump supply (VP) allows extended  
tuning voltage in 3 V systems  
Programmable dual-modulus prescaler  
8/9, 16/17, 32/33, 64/65  
Programmable charge pump currents  
Programmable antibacklash pulse width  
3-wire serial interface  
Analog and digital lock detect  
Hardware and software power-down mode  
The ADF4106 frequency synthesizer can be used to implement  
local oscillators in the up-conversion and down-conversion  
sections of wireless receivers and transmitters. It consists of a  
low noise, digital phase frequency detector (PFD), a precision  
charge pump, a programmable reference divider, programmable  
A counter and B counter, and a dual-modulus prescaler (P/P + 1).  
The A (6-bit) counter and B (13-bit) counter, in conjunction  
with the dual-modulus prescaler (P/P + 1), implement an N  
divider (N = BP + A). In addition, the 14-bit reference counter  
(R Counter) allows selectable REFIN frequencies at the PFD  
input. A complete phase-locked loop (PLL) can be implemented  
if the synthesizer is used with an external loop filter and voltage  
controlled oscillator (VCO). Its very high bandwidth means  
that frequency doublers can be eliminated in many high  
frequency systems, simplifying system architecture and  
reducing cost.  
APPLICATIONS  
Broadband wireless access  
Satellite systems  
Instrumentation  
Wireless LANS  
Base stations for wireless radios  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DV  
R
SET  
V
CPGND  
DD  
DD  
P
REFERENCE  
14-BIT  
R COUNTER  
PHASE  
FREQUENCY  
DETECTOR  
REF  
CHARGE  
PUMP  
IN  
CP  
14  
R COUNTER  
LATCH  
LOCK  
DETECT  
CURRENT  
SETTING 2  
CURRENT  
SETTING 1  
CLK  
DATA  
LE  
24-BIT INPUT  
REGISTER  
FUNCTION  
LATCH  
CPI6 CPI5 CPI4  
HIGH Z  
CPI3 CPI2 CPI1  
22  
A, B COUNTER  
LATCH  
FROM  
SD  
19  
OUT  
AV  
FUNCTION  
LATCH  
DD  
MUXOUT  
MUX  
13  
13-BIT  
N = BP + A  
SD  
OUT  
B COUNTER  
LOAD  
RF  
RF  
A
B
PRESCALER  
P/P + 1  
IN  
IN  
LOAD  
M3 M2 M1  
6-BIT  
A COUNTER  
ADF4106  
6
CE  
AGND  
DGND  
Figure 1.  
Rev. E  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2001–2012 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  

ADF4106BCPZ 替代型号

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