ADF4002BCPZ-RL7

更新时间： 2024-01-01 18:20:42

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	457K
描述
Phase Detector/Frequency Synthesizer

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数据手册
替代型号

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ADF4002BCPZ-RL7 数据手册

ADF4002

Digital lock detect is active high. When LDP in the R counter

latch is set to 0, digital lock detect is set high when the phase

error on three consecutive phase detector (PD) cycles is less

than 15 ns. With LDP set to 1, five consecutive cycles of less

than 15 ns are required to set the lock detect. It stays set at high

until a phase error of greater than 25 ns is detected on any

subsequent PD cycle. For PFD frequencies greater than 10 MHz,

analog lock detect is more accurate because of the smaller pulse

widths.

CHARGE

PUMP

R DIVIDER

CLR1

PROGRAMMABLE

DELAY

ABP2

ABP1

The N-channel, open-drain, analog lock detect should be

operated with an external pull-up resistor of 10 kΩ nominal.

When lock has been detected this output is high with narrow,

low-going pulses.

CLR2

D2 Q2

DOWN

N DIVIDER

CPGND

Figure 14. PFD Simplified Schematic and Timing (In Lock)

INPUT SHIFT REGISTER

MUXOUT AND LOCK DETECT

The ADF4002 digital section includes a 24-bit input shift

clocked into the 24-bit shift register on each rising edge of CLK.

The data is clocked in MSB-first. Data is transferred from the

shift register to one of four latches on the rising edge of LE. The

destination latch is determined by the state of the two control

bits (C2, C1) in the shift register. These are the two LSBs, DB1

and DB0, as shown in the timing diagram (see Figure 2). Table 6

provides the truth table for these bits. Figure 16 shows a

summary of how the latches are programmed.

The output multiplexer on the ADF4002 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function

latch. Figure 19 shows the full truth table. Figure 15 shows the

MUXOUT section in block diagram form.

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

Table 6. C2, C1 Truth Table

Control Bits

MUX

CONTROL

MUXOUT

Data Latch

R Counter

N Counter

Function Latch

Initialization Latch

DGND

Figure 15. MUXOUT Circuit

Lock Detect

MUXOUT can be programmed for two types of lock detect:

digital lock detect and analog lock detect.

Rev. 0 | Page 9 of 24

1...6 7 8910 11 12...24

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ADF4002BCPZ-RL7 替代型号

型号	品牌	替代类型	描述	数据表
ADF4002BCPZ-RL	ADI	类似代替	Phase Detector/Frequency Synthesizer
ADF4002BCPZ	ADI	类似代替	Phase Detector/Frequency Synthesizer

与ADF4002BCPZ-RL7相关器件

型号	品牌	获取价格	描述	数据表
ADF4002BRUZ	ADI	获取价格	Phase Detector/Frequency Synthesizer
ADF4002BRUZ-RL	ADI	获取价格	Phase Detector/Frequency Synthesizer
ADF4002BRUZ-RL7	ADI	获取价格	Phase Detector/Frequency Synthesizer
ADF4002SRU-EP	ADI	获取价格	Phase Detector / PLL Frequency Synthesizer
ADF4002SRUZ-EP	ADI	获取价格	Phase Detector / PLL Frequency Synthesizer
ADF4002SRUZ-EP-RL7	ADI	获取价格	Phase Detector / PLL Frequency Synthesizer
ADF4007	ADI	获取价格	High Frequency Divider/PLL Synthesizer
ADF4007BCP	ADI	获取价格	High Frequency Divider/PLL Synthesizer
ADF4007BCP	ROCHESTER	获取价格	PLL FREQUENCY SYNTHESIZER, 7500 MHz, QCC20, MO-220-VGGD-1, LFCSP-20
ADF4007BCP-REEL	ADI	获取价格	High Frequency Divider/PLL Synthesizer

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