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ADCLK946/PCBZ PDF预览

ADCLK946/PCBZ

更新时间: 2024-02-11 09:46:16
品牌 Logo 应用领域
亚德诺 - ADI 时钟
页数 文件大小 规格书
12页 354K
描述
Six LVPECL Outputs, SiGe Clock Fanout Buffer

ADCLK946/PCBZ 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC24,.16SQ,20针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.83
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/579004.3.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=579004
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=5790043D View:https://componentsearchengine.com/viewer/3D.php?partID=579004
Samacsys PartID:579004Samacsys Image:https://componentsearchengine.com/Images/9/ADCLK946BCPZ.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/3/ADCLK946BCPZ.jpgSamacsys Pin Count:25
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:CP-24-2-+-+Samacsys Released Date:2017-01-11 11:21:59
Is Samacsys:N系列:946
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:24实输出次数:6
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:0.22 ns
传播延迟(tpd):0.22 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.28 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BIPOLAR
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:4 mmBase Number Matches:1

ADCLK946/PCBZ 数据手册

 浏览型号ADCLK946/PCBZ的Datasheet PDF文件第6页浏览型号ADCLK946/PCBZ的Datasheet PDF文件第7页浏览型号ADCLK946/PCBZ的Datasheet PDF文件第8页浏览型号ADCLK946/PCBZ的Datasheet PDF文件第9页浏览型号ADCLK946/PCBZ的Datasheet PDF文件第10页浏览型号ADCLK946/PCBZ的Datasheet PDF文件第12页 
ADCLK946  
INPUT TERMINATION OPTIONS  
V
CC  
V
V
REF  
REF  
V
V
T
T
50  
50Ω  
50  
50Ω  
CLK  
CLK  
CLK  
CLK  
CONNECT V TO V  
CC  
.
CONNECT V TO V  
.
REF  
T
T
Figure 19. Interfacing to CML Inputs  
Figure 21. AC-Coupling Differential Signals Inputs, Such as LVDS  
V
REF  
V
T
50  
50Ω  
V
REF  
CLK  
V
T
CLK  
50Ω  
50Ω  
V
– 2V  
CC  
CLK  
CLK  
CONNECT V , V  
, AND CLK. PLACE A BYPASS  
CAPACITOR FROM V TO GROUND.  
T
REF  
T
ALTERNATIVELY, V , V  
, AND CLK CAN BE  
T
REF  
CONNECTED, GIVING A CLEANER LAYOUT AND  
A 180° PHASE SHIFT.  
CONNECT V TO V 2V.  
CC  
T
Figure 20. Interfacing to PECL Inputs  
Figure 22. Interfacing to AC-Coupled Single-Ended Inputs  
Rev. 0 | Page 11 of 12  
 

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