ADCLK946/PCBZ

更新时间： 2024-01-08 19:19:57

品牌	Logo	应用领域
亚德诺 - ADI		时钟
页数	文件大小	规格书
12页	354K
描述
Six LVPECL Outputs, SiGe Clock Fanout Buffer

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技术参数
数据手册

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ADCLK946/PCBZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC24,.16SQ,20	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.83
Samacsys Confidence：	3	Samacsys Status：	Released
2D Presentation：	https://componentsearchengine.com/2D/0T/579004.3.1.png	Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=579004
PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=579004	3D View：	https://componentsearchengine.com/viewer/3D.php?partID=579004
Samacsys PartID：	579004	Samacsys Image：	https://componentsearchengine.com/Images/9/ADCLK946BCPZ.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/3/ADCLK946BCPZ.jpg	Samacsys Pin Count：	25
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Quad Flat No-Lead
Samacsys Footprint Name：	CP-24-2-+-+	Samacsys Released Date：	2017-01-11 11:21:59
Is Samacsys：	N	系列：	946
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-XQCC-N24
JESD-609代码：	e3	长度：	4 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	6
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC24,.16SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	Prop。Delay @ Nom-Sup：	0.22 ns
传播延迟（tpd）：	0.22 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.28 ns	座面最大高度：	1 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	2.97 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	4 mm	Base Number Matches：	1

ADCLK946/PCBZ 数据手册

ADCLK946

ensure that the pins are within the rated input differential and

common-mode ranges.

PCB LAYOUT CONSIDERATIONS

The ADCLK946 buffer is designed for very high speed

applications. Consequently, high speed design techniques must

be used to achieve the specified performance. It is critically

important to use low impedance supply planes for both the

negative supply (V_EE) and the positive supply (V_CC) planes as

part of a multilayer board. Providing the lowest inductance

return path for switching currents ensures the best possible

performance in the target application.

If the return is floated, the device exhibits a 100 ꢁ cross-

termination, but the source must then control the common-

mode voltage and supply the input bias currents.

There are ESD/clamp diodes between the input pins to prevent

the application from developing excessive offsets to the input

transistors. ESD diodes are not optimized for best ac perfor-

mance. When a clamp is required, it is recommended that

appropriate external diodes be used.

The following references to the ground plane assume that

the V_EEpower plane is grounded for LVPECL operation.

Note that, for ECL operation, the V_CCpower plane becomes

the ground plane.

Exposed Metal Paddle

The exposed metal paddle on the ADCLK946 package is both

an electrical connection and a thermal enhancement. For the

device to function properly, the paddle must be properly

attached to the V_EEpin.

It is also important to adequately bypass the input and output

supplies. Place a 1 μF electrolytic bypass capacitor within several

inches of each V_CCpower supply pin to the ground plane. In

addition, place multiple high quality 0.001 μF bypass capacitors

as close as possible to each of the V_CCsupply pins, and connect

the capacitors to the ground plane with redundant vias.

Carefully select high frequency bypass capacitors for minimum

inductance and ESR. To improve the effectiveness of the bypass

at high frequencies, minimize parasitic layout inductance. Also,

avoid discontinuities along input and output transmission lines

that can affect jitter performance.

When properly mounted, the ADCLK946 also dissipates heat

through its exposed paddle. The PCB acts as a heat sink for the

ADCLK946. The PCB attachment must provide a good thermal

path to a larger heat dissipation area. This requires a grid of vias

from the top layer down to the V_EEpower plane (see Figure 18).

The ADCLK946 evaluation board (ADCLK946/PCBZ)

provides an example of how to attach the part to the PCB.

In a 50 Ω environment, input and output matching have a

significant impact on performance. The buffer provides internal

CLK

50 Ω termination resistors for both CLK and

inputs.

VIAS TO V POWER

Normally, the return side is connected to the reference pin that is

provided. Carefully bypass the termination potential using

ceramic capacitors to prevent undesired aberrations on the

input signal due to parasitic inductance in the termination

return path. If the inputs are dc-coupled to a source, take care to

PLANE

Figure 18. PCB Land for Attaching Exposed Paddle

Rev. 0 | Page 10 of 12

1...7 8 91011 12

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与ADCLK946/PCBZ相关器件

型号	品牌	描述	获取价格	数据表
ADCLK946BCPZ	ADI	Six LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK946BCPZ-REEL7	ADI	Six LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK948	ADI	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK948/PCBZ	ADI	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK948BCPZ	ADI	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK948BCPZ-REEL7	ADI	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格

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