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ADC14155CISQ PDF预览

ADC14155CISQ

更新时间: 2024-11-26 04:31:19
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器模数转换器PC
页数 文件大小 规格书
19页 723K
描述
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter

ADC14155CISQ 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48Reach Compliance Code:not_compliant
ECCN代码:3A991.C.3HTS代码:8542.39.00.01
风险等级:5.4Is Samacsys:N
最大模拟输入电压:2.6 V最小模拟输入电压:
最长转换时间:0.006 µs转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-XQCC-N48JESD-609代码:e0
长度:7 mm最大线性误差 (EL):0.0238%
湿度敏感等级:3模拟输入通道数量:1
位数:14功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC48,.27SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:1.8,3.3 V
认证状态:Not Qualified采样速率:155 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:0.8 mm
子类别:Analog to Digital Converters标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mmBase Number Matches:1

ADC14155CISQ 数据手册

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PRELIMINARY  
May 2006  
ADC14155  
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter  
General Description  
Features  
n 1.1 GHz Full Power Bandwidth  
n Internal sample-and-hold circuit  
n Low power consumption  
The ADC14155 is a high-performance CMOS analog-to-  
digital converter capable of converting analog input signals  
into 14-bit digital words at rates up to 155 Mega Samples Per  
Second (MSPS). This converter uses a differential, pipelined  
architecture with digital error correction and an on-chip  
sample-and-hold circuit to minimize power consumption and  
the external component count, while providing excellent dy-  
namic performance. A unique sample-and-hold stage yields  
a full-power bandwidth of 1.1 GHz. The ADC14155 operates  
from dual +3.3V and +1.8V power supplies and consumes  
974 mW of power at 155 MSPS.  
n Internal precision 1.0V reference  
n Single-ended or Differential clock modes  
n Data Ready output clock  
n Clock Duty Cycle Stabilizer  
n Dual +3.3V and +1.8V supply operation (+/- 10%)  
n Power-down mode  
n Offset binary or 2’s complement output data format  
n 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)  
The separate +1.8V supply for the digital output interface  
allows lower power operation with reduced noise. A power-  
down feature reduces the power consumption to 5 mW with  
the clock input disabled, while still allowing fast wake-up time  
to full operation.  
Key Specifications  
n Resolution  
14 Bits  
n Conversion Rate  
155 MSPS  
71.4 dBFS (typ)  
85.3 dBFS (typ)  
11.5 bits (typ)  
1.1 GHz (typ)  
974 mW (typ)  
The differential inputs provide a full scale differential input  
swing equal to 2 times the reference voltage. A stable 1.0V  
internal voltage reference is provided, or the ADC14155 can  
be operated with an external reference.  
n SNR (fIN = 70 MHz)  
n SFDR (fIN = 70 MHz)  
n ENOB (fIN = 70 MHz)  
n Full Power Bandwidth  
n Power Consumption  
For optimum performance, it is recommended to operate the  
ADC14155 with a differential clock input, which doubles the  
clock amplitude compared with single-ended clock opera-  
tion. Clock mode (differential versus single-ended) and out-  
put data format (offset binary versus 2’s complement) are  
pin-selectable. A duty cycle stabilizer maintains performance  
over a wide range of clock duty cycles.  
Applications  
n High IF Sampling Receivers  
n Wireless Base Station Receivers  
n Power Amplifier Linearization  
n Multi-carrier, Multi-mode Receivers  
n Test and Measurement Equipment  
n Communications Instrumentation  
n Radar Systems  
The ADC14155 is available in a 48-lead LLP package and  
operates over the industrial temperature range of −40˚C to  
+85˚C.  
© 2006 National Semiconductor Corporation  
DS201790  
www.national.com  

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