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ADC1415S125 PDF预览

ADC1415S125

更新时间: 2024-11-26 08:18:47
品牌 Logo 应用领域
恩智浦 - NXP 双倍数据速率
页数 文件大小 规格书
33页 175K
描述
Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer CMOS or LVDS DDR digital outputs

ADC1415S125 数据手册

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ADC1415S065/080/105/125  
Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer  
CMOS or LVDS DDR digital outputs  
Rev. 02 — 4 June 2009  
Objective data sheet  
1. General description  
The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for  
high dynamic performances and low power consumption at sample rates up to 125 Msps.  
Pipelined architecture and output error correction ensure the ADC1415S is accurate  
enough to guarantee zero missing codes over the entire operating range. Supplied from a  
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,  
thanks to a separate digital output supply.  
The ADC1415S supports the LVDS (Low Voltage Differential Signalling) DDR (Double  
Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user  
to easily configure the ADC.  
The device also includes a programmable gain amplifier with a flexible input voltage  
range. With excellent dynamic performance from the baseband to input frequencies of  
170 MHz or more, the ADC1415S is ideal for use in communications, imaging and  
medical applications - especially in high Intermediate Frequency (IF) applications thanks  
to the integrated input buffer. The input buffer ensures that the input impedance remains  
constant and low and the performance consistent over a wide frequency range.  
2. Features  
I SNR, 73 dB / SFDR, 90 dBc  
I Pin compatible with the  
ADC1410S065/080/105/125  
I Sample rate up to 125 Msps  
I 14-bit pipelined ADC core  
I Integrated input buffer  
I Input bandwidth, 600 MHz  
I Power dissipation, 587 mW at 80 Msps,  
including analog input buffer  
I SPI Interface  
I Duty cycle stabilizer  
I Fast OTR detection  
I Flexible input voltage range: 1 V (p-p) to I Offset binary, 2’s complement, gray  
2 V (p-p) with 6 dB programmable  
fine gain  
code  
I CMOS or LVDS DDR digital outputs  
I INL ±1 LSB, DNL ±0.5 LSB (typical)  
I Power-down and Sleep modes  
I HVQFN40 package  
3. Applications  
I Wireless and wired broadband communications  
I Spectral analysis  
I Ultrasound equipment  
I Portable instrumentation  
I Imaging systems  

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