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ADC1415S105HN/C1,5 PDF预览

ADC1415S105HN/C1,5

更新时间： 2024-11-26 15:29:03
品牌 Logo 应用领域
恩智浦 - NXP 转换器
页数 文件大小 规格书
42页 270K
描述
IC IC,A/D CONVERTER,SINGLE,14-BIT,LLCC,40PIN, Analog to Digital Converter

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ADC1415S105HN/C1,5 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：ObsoleteReach Compliance Code：unknown
ECCN代码：3A991.C.3HTS代码：8542.39.00.01
风险等级：5.82转换器类型：A/D CONVERTER
JESD-30 代码：S-PQCC-N40JESD-609代码：e3
最大线性误差 (EL)：0.03%湿度敏感等级：1
位数：14功能数量：1
端子数量：40最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC40,.24SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/5 V认证状态：Not Qualified
子类别：Analog to Digital Converters表面贴装：YES
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

ADC1415S105HN/C1,5 数据手册

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ADC1415S series  
Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps  
with input buffer; CMOS or LVDS DDR digital outputs  
Rev. 4 — 17 December 2010  
Product data sheet  
1. General description  
The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for  
high dynamic performance and low power consumption at sample rates up to 125 Msps.  
Pipelined architecture and output error correction ensure the ADC1415S is accurate  
enough to guarantee zero missing codes over the entire operating range. Supplied from a  
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,  
thanks to a separate digital output supply.  
The ADC1415S supports the Low Voltage Differential Signalling (LVDS) Double Data  
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the  
user to easily configure the ADC.  
The device also includes a SPI programmable full-scale to allow flexible input voltage  
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the  
baseband to input frequencies of 170 MHz or more, the ADC1415S is ideal for use in  
communications, imaging and medical applications - especially in high Intermediate  
Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures  
that the input impedance remains constant and low and the performance consistent over  
a wide frequency range.  
2. Features and benefits  
„ SNR, 72 dBFS; SFDR, 86 dBc  
„ Input bandwidth, 600 MHz  
„ Power dissipation, 635 mW at 80 Msps,  
including analog input buffer  
„ Sample rate up to 125 Msps  
„ 14-bit pipelined ADC core  
„ Clock input divided by 2 for less jitter  
contribution  
„ Serial Peripheral Interface (SPI)  
„ Duty cycle stabilizer  
„ Integrated input buffer  
„ Fast OuT-of-Range (OTR) detection  
„ Flexible input voltage range: 1 V (p-p) to „ Offset binary, two’s complement, gray  
2 V (p-p)  
code  
„ CMOS or LVDS DDR digital outputs  
„ Power-down mode and Sleep mode  
„ Pin compatible with ADC1215S series, „ HVQFN40 package  
ADC1015S series and the  
ADC1115S125  
 
 
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