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ADC12L066CIVY PDF预览

ADC12L066CIVY

更新时间: 2024-11-25 22:28:35
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器模数转换器
页数 文件大小 规格书
27页 750K
描述
12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold

ADC12L066CIVY 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:LQFP-32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.44最大模拟输入电压:3.1 V
最小模拟输入电压:最长转换时间:0.09 µs
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
最大线性误差 (EL):0.0659%湿度敏感等级:3
模拟输入通道数量:1位数:12
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
采样速率:66 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.6 mm子类别:Analog to Digital Converters
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:7 mm
Base Number Matches:1

ADC12L066CIVY 数据手册

 浏览型号ADC12L066CIVY的Datasheet PDF文件第2页浏览型号ADC12L066CIVY的Datasheet PDF文件第3页浏览型号ADC12L066CIVY的Datasheet PDF文件第4页浏览型号ADC12L066CIVY的Datasheet PDF文件第5页浏览型号ADC12L066CIVY的Datasheet PDF文件第6页浏览型号ADC12L066CIVY的Datasheet PDF文件第7页 
December 2003  
ADC12L066  
12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with  
Internal Sample-and-Hold  
General Description  
Features  
n Single supply operation  
n Low power consumption  
n Power down mode  
n On-chip reference buffer  
The ADC12L066 is a monolithic CMOS analog-to-digital con-  
verter capable of converting analog input signals into 12-bit  
digital words at 66 Megasamples per second (MSPS), mini-  
mum, with typical operation possible up to 80 MSPS. This  
converter uses a differential, pipeline architecture with digital  
error correction and an on-chip sample-and-hold circuit to  
minimize die size and power consumption while providing  
excellent dynamic performance. A unique sample-and-hold  
stage yields a full-power bandwidth of 450 MHz. Operating  
on a single 3.3V power supply, this device consumes just  
357 mW at 66 MSPS, including the reference current. The  
Power Down feature reduces power consumption to just  
50 mW.  
Key Specifications  
n Resolution  
n Conversion Rate  
n Full Power Bandwidth  
n DNL  
n SNR (fIN = 10 MHz)  
n SFDR (fIN = 10 MHz)  
n Data Latency  
12 Bits  
66 MSPS  
450 MHz  
0.4 LSB (typ)  
66 dB (typ)  
80 dB (typ)  
The differential inputs provide a full scale input swing equal  
to VREF with the possibility of a single-ended input. Full use  
of the differential input is recommended for optimum perfor-  
mance. For ease of use, the buffered, high impedance,  
single-ended reference input is converted on-chip to a differ-  
ential reference for use by the processing circuitry. Output  
data format is 12-bit offset binary.  
6 Clock Cycles  
+3.3V 300 mV  
357 mW (typ)  
n Supply Voltage  
n Power Consumption, 66 MHz  
Applications  
n Ultrasound and Imaging  
n Instrumentation  
n Cellular Base Stations/Communications Receivers  
n Sonar/Radar  
This device is available in the 32-lead LQFP package and  
will operate over the industrial temperature range of −40˚C to  
+85˚C. An evaluation board is available to facilitate the  
evaluation process.  
n xDSL  
n Wireless Local Loops  
n Data Acquisition Systems  
n DSP Front Ends  
Connection Diagram  
20032801  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2003 National Semiconductor Corporation  
DS200328  
www.national.com  

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