Datasheet > ADC12QJ800-Q1

ADC12QJ800-Q1

更新时间： 2024-11-27 02:48:59

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
151页	6801K
描述
ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface

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ADC12QJ800-Q1 数据手册

ADC12QJ800, ADC12DJ800, ADC12SJ800

SBASAG0 – OCTOBER 2021

ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit,

Analog-to-Digital Converter (ADC) with JESD204C Interface

1 Features

2 Applications

•

ADC Core:

– Resolution: 12 Bit

– Maximum sampling rate: 800 MSPS

– Non-interleaved architecture

– Internal dither reduces high-order harmonics

Performance specifications (–1 dBFS):

– SNR (97 MHz): 57.6 dBFS

•

Light detection and ranging (LiDAR)

Handheld test equipment

Multi-channel oscilloscopes and digitizers

Wireless communications test equipment

Optical coherent tomography (OCT)

Electronic warfare (SIGINT, ELINT)

Satellite communications (SATCOM)

•

– ENOB (97 MHz): 9.0 Bits

– SFDR (97 MHz): 62 dBFS

– Noise floor (–20 dBFS): –146.1 dBFS/Hz

Full-scale input voltage: 800 mV_PP-DIFF

Full-power input bandwidth: 6 GHz

JESD204C Serial data interface:

– Support for 2 to 8 (Quad/Dual channel) or 1 to 4

(Single channel) total SerDes lanes

– Maximum baud-rate: 17.16 Gbps

– 64B/66B and 8B/10B encoding modes

– Subclass-1 support for deterministic latency

– Compatible with JESD204B receivers

Optional internal sampling clock generation

– Internal PLL and VCO (7.2–8.2 GHz)

SYSREF Windowing eases synchronization

Four clock outputs simplify system clocking

– Reference clocks for FPGA or adjacent ADC

– Reference clock for SerDes transceivers

Timestamp input and output for pulsed systems

Power consumption (800 MSPS):

3 Description

ADC12xJ800 is

family of quad, dual and

single channel, 12-bit, 800 MSPS analog-to-digital

converters (ADC). Low power consumption, high

sampling rate and 12-bit resolution makes the

ADC12xJ800 ideally suited for a variety of multi-

channel communications and test systems.

•

Full-power input bandwidth (-3 dB) of 6 GHz enables

direct RF sampling of of L-band and S-band.

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

•

ADC12QJ800

ADC12DJ800

ADC12SJ800

FCBGA (144) 10.0 mm × 10.0 mm

•

(1) For all available packages, see the package option

addendum at the end of the data sheet.

•

– Quad Channel: 415 mW / channel

– Dual channel: 555 mW / channel

– Single channel: 830 mW

•

Power supplies: 1.1 V, 1.9 V

Quad Channel Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...151

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与ADC12QJ800-Q1相关器件

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ADC-12QU/BIN	ADI	获取价格	IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, DMA72, MODULE-72, Analog to Digita
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