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ADC12SJ1600AAV PDF预览

ADC12SJ1600AAV

更新时间： 2024-11-27 02:48:59
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德州仪器 - TI /
页数 文件大小 规格书
156页 6869K
描述
ADC12xJ1600 Quad, Dual, or Single Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface

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ADC12SJ1600AAV 数据手册

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ADC12QJ1600, ADC12DJ1600, ADC12SJ1600  
SBASAE0 – OCTOBER 2021  
ADC12xJ1600 Quad, Dual, or Single Channel 1.6-GSPS, 12-Bit, Analog-to-Digital  
Converter (ADC) with JESD204C Interface  
1 Features  
2 Applications  
•
ADC Core:  
– Resolution: 12 Bit  
– Maximum sampling rate: 1.6 GSPS  
– Non-interleaved architecture  
– Internal dither reduces high-order harmonics  
Performance specifications (–1 dBFS):  
– SNR (100 MHz): 57.4 dBFS  
•
•
•
•
•
•
•
Light detection and ranging (LiDAR)  
Handheld test equipment  
Multi-channel oscilloscopes and digitizers  
Wireless communications test equipment  
Optical coherent tomography (OCT)  
Electronic warfare (SIGINT, ELINT)  
Satellite communications (SATCOM)  
•
– ENOB (100 MHz): 9.1 Bits  
– SFDR (100 MHz): 64 dBc  
3 Description  
ADC12xJ1600 is a family of quad, dual and single  
channel, 12-bit, 1.6 GSPS analog-to-digital converters  
(ADC). Low power consumption, high sampling rate  
and 12-bit resolution makes the ADC12xJ1600 ideally  
suited for a variety of multi-channel communications  
and test systems.  
– Noise floor (–20 dBFS): –147 dBFS  
Full-scale input voltage: 800 mVPP-DIFF  
Full-power input bandwidth: 6 GHz  
JESD204C Serial data interface:  
•
•
•
– Support for 2 to 8 (Quad/Dual channel) or 1 to 4  
(Single channel) total SerDes lanes  
– Maximum baud-rate: 17.16 Gbps  
– 64B/66B and 8B/10B encoding modes  
– Subclass-1 support for deterministic latency  
– Compatible with JESD204B receivers  
Optional internal sampling clock generation  
– Internal PLL and VCO (7.2–8.2 GHz)  
SYSREF Windowing eases synchronization  
Four clock outputs simplify system clocking  
– Reference clocks for FPGA or adjacent ADC  
– Reference clock for SerDes transceivers  
Timestamp input and output for pulsed systems  
Power consumption (1 GSPS):  
Full-power input bandwidth (-3 dB) of 6 GHz enables  
direct RF sampling of of L-band and S-band.  
Device Information  
PART NUMBER  
PACKAGE(1)  
BODY SIZE (NOM)  
•
ADC12QJ1600  
ADC12DJ1600  
ADC12SJ1600  
FCBGA (144) 10.0 mm × 10.0 mm  
•
•
(1) For all available packages, see the package option  
addendum at the end of the data sheet.  
•
•
TMSTP+  
TMSTPt  
÷
TRIGOUT+  
TRIGOUTt  
INA+  
– Quad Channel: 477 mW / channel  
– Dual channel: 700 mW / channel  
– Single channel: 1000 mW  
ADC A  
ADC B  
ADC C  
ADC D  
Timestamp  
Insertion  
SerDes  
PLL  
INAt  
D0+  
D0t  
INB+  
Timestamp  
Insertion  
INBt  
•
Power supplies: 1.1 V, 1.9 V  
JESD204B/C  
INC+  
D7+  
Timestamp  
Insertion  
INCt  
D7t  
IND+  
Timestamp  
Insertion  
SYNCSE\  
INDt  
CLK+  
CALTRIG  
CALSTAT  
Calibration  
Controller  
CLKt  
OVRA  
OVRB  
PLL  
+VCO  
SE_CLK  
Status  
Indicators  
OVRC  
÷
÷
SYSREF+  
SYSREF  
Windowing  
To synchronization logic  
OVRD  
SYSREFt  
PLLREFO+  
PLLEN  
PLLREFOt  
PLLREFSE  
CLKCFG0  
Clock  
Control  
SCLK  
CLKCFG1  
Serial  
Programming  
Interface  
SCS  
SDI  
SDO  
Quad Channel Block Diagram  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
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