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ADC12V170

更新时间： 2024-02-09 00:42:14
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
22页 562K
描述
12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs

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ADC12V170 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC48,.27SQ,20针数：48
Reach Compliance Code：compliantECCN代码：3A001.A.5.A.3
HTS代码：8542.39.00.01风险等级：1.27
最大模拟输入电压：2.6 V最小模拟输入电压：-2 V
最长转换时间：1.5 µs转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-PQCC-N48JESD-609代码：e3
长度：7 mm最大线性误差 (EL)：0.0464%
湿度敏感等级：3模拟输入通道数量：1
位数：12功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified采样速率：170 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：0.8 mm
子类别：Analog to Digital Converters最大压摆率：289 mA
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

ADC12V170 数据手册

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October 2007  
ADC12V170  
12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with  
LVDS Outputs  
General Description  
Features  
The ADC12V170 is a high-performance CMOS analog-to-  
digital converter with LVDS outputs. It is capable of converting  
analog input signals into 12-Bit digital words at rates up to 170  
Mega Samples Per Second (MSPS). Data leaves the chip in  
a DDR (Dual Data Rate) format; this allows both edges of the  
output clock to be utilized while achieving a smaller package  
size. This converter uses a differential, pipelined architecture  
with digital error correction and an on-chip sample-and-hold  
circuit to minimize power consumption and the external com-  
ponent count, while providing excellent dynamic perfor-  
mance. A unique sample-and-hold stage yields a full-power  
bandwidth of 1.1 GHz. The ADC12V170 operates from dual  
+3.3V and +1.8V power supplies and consumes 781 mW of  
power at 170 MSPS.  
1.1 GHz Full Power Bandwidth  
■
■
■
■
■
■
■
■
Internal sample-and-hold circuit  
Internal precision 1.0V reference  
Single-ended or Differential clock modes  
Clock Duty Cycle Stabilizer  
Dual +3.3V and +1.8V supply operation  
Power-down and Sleep modes  
Offset binary or 2's complement output data format  
LVDS outputs  
■
■
Pin-compatible: ADC14V155  
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)  
■
The separate +1.8V supply for the digital output interface al-  
lows lower power operation with reduced noise. A power-  
down feature reduces the power consumption to 15 mW while  
still allowing fast wake-up time to full operation. In addition  
there is a sleep feature which consumes 50 mW of power and  
has a faster wake-up time.  
Key Specifications  
Resolution  
12 Bits  
■
■
■
■
■
■
■
Conversion Rate  
170 MSPS  
67.2 dBFS (typ)  
85.8 dBFS (typ)  
10.9 bits (typ)  
1.1 GHz (typ)  
781 mW (typ)  
SNR (fIN = 70 MHz)  
SFDR (fIN = 70 MHz)  
ENOB (fIN = 70 MHz)  
Full Power Bandwidth  
Power Consumption  
The differential inputs provide a full scale differential input  
swing equal to 2 times the reference voltage. A stable 1.0V  
internal voltage reference is provided, or the ADC12V170 can  
be operated with an external reference.  
Clock mode (differential versus single-ended) and output data  
format (offset binary versus 2's complement) are pin-se-  
lectable. A duty cycle stabilizer maintains performance over  
a wide range of input clock duty cycles.  
Applications  
High IF Sampling Receivers  
■
■
■
■
■
■
Wireless Base Station Receivers  
Power Amplifier Linearization  
The ADC12V170 is pin-compatible with the ADC14V155. It is  
available in a 48-lead LLP package and operates over the  
industrial temperature range of −40°C to +85°C.  
Multi-carrier, Multi-mode Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Radar Systems  
■
Block Diagram  
30016802  
© 2007 National Semiconductor Corporation  
300168  
www.national.com  
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