Mixed-Signal Front End
for Broadband Applications
AD9878
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low cost 3.3 V CMOS MxFE™ for broadband applications
DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+®)
I
12
–1
16
SINC
Tx
DAC
TxID[5:0]
Q
Tx
DDS
Σ-∆
Σ-∆ OUTPUT
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
Analog Tx output level adjust
3
4
CA PORT
MCLK
SDIO
CONTROL REGISTERS
PLL
OSCIN
Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input
10-bit, 29 MSPS sampling ADC
8-bit ∑-∆ auxiliary DAC
10
IF10[4:0]
IF10 INPUT
ADC
MUX
MUX
12
IF12B INPUT
VIDEO IN
ADC
MUX
Direct interface to AD832x family of PGA cable drivers
Σ
APPLICATIONS
–
IF12[11:0]
FLAG[2:1]
CLAMP
LEVEL
Cable set-top boxes
Cable and wireless modems
MUX
12
IF12A INPUT
ADC
Figure 1.
GENERAL DESCRIPTION
The AD9878 is a single-supply, cable modem/set-top box,
mixed-signal front end. The device contains a transmit path
interpolation filter, a complete quadrature digital upconverter,
and a transmit DAC. The receive path contains dual 12-bit
ADCs and a 10-bit ADC. All internally required clocks and an
output system clock are generated by the phase-locked loop
(PLL) from a single crystal oscillator or clock input.
The 12-bit ADCs provide excellent undersampling performance,
allowing this device to typically deliver better than 10 ENOBs
with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at
rates up to 29 MHz, allowing them to process wideband signals.
The AD9878 includes a programmable ∑-∆ DAC, which can be
used to control an external component such as a variable gain
amplifier (VGA) or a voltage controlled tuner.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth up to 4.35 MHz.
Carrier frequencies up to 65 MHz with 26 bits of frequency tuning
resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits and can run at
sampling rates as high as 232 MSPS. Analog output scaling from
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
The AD9878 also integrates a CA port that enables a host
processor to interface with the AD832x family of programmable
gain amplifier (PGA) cable drivers or industry equivalent via
the MxFE serial port (SPORT).
The AD9878 is available in a 100-lead, LQFP package. The
AD9878 is specified over the extended industrial (−40°C to
+85°C) temperature range.
Rev. A
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