CMOS 200 MSPS 14-Bit
Quadrature Digital Upconverter
AD9857
FEATURES
200 MHz internal clock rate
3.3 V single supply
14-bit data path
Single-ended or differential input reference clock
80-lead LQFP surface-mount packaging
Three modes of operation:
Quadrature modulator mode
Single-tone mode
Excellent dynamic performance:
80 dB SFDR @ 65 MHz ( 100 kHz) AOUT
4× to 20× programmable reference clock multiplier
Reference clock multiplier PLL lock detect indicator
Internal 32-bit quadrature DDS
FSK capability
8-bit output amplitude control
Single-pin power-down function
Four programmable, pin-selectable signal profiles
SIN(x)/x correction (inverse SINC function)
Simplified control interface
Interpolating DAC mode
APPLICATIONS
HFC data, telephony, and video modems
Wireless base station
Agile, LO frequency synthesis
Broadband communications
10 MHz serial, 2-wire or 3-wire SPI®-compatible
FUNCTIONAL BLOCK DIAGRAM
INVERSE
CIC FILTER
FIXED
INTER-
POLATOR
AD9857
QUADRATURE
MODULATOR
DAC_RSET
I
PROGRAMMABLE
INTERPOLATOR
14
14
PARALLEL
DATA IN
(14-BIT)
IOUT
IOUT
CIC
(2 - 63 )
14-BIT
DAC
INV
CIC
(4 )
14
Q
INVERSE
SINC
FILTER
8
OUTPUT
SCALE
VALUE
DDS
CORE
TUNING
WORD
32
TIMING AND CONTROL
CONTROL REGISTERS
POWER-
DOWN
LOGIC
PROFILE
SELECT
LOGIC
REFCLK
REFCLK
CLOCK
MULTIPLIER
(4 – 20 )
MODE
CONTROL
PDCLK/ TxENABLE RESET
FUD
CIC
OVERFLOW
SERIAL
PORT
DIGITAL PS1 PS0
POWER-
DOWN
PLL
LOCK
CLOCK
INPUT
MODE
Figure 1.
Rev. C
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