1 GSPS
Direct Digital Synthesizer
AD9858
FEATURES
1 GSPS internal clock speed
GENERAL DESCRIPTION
The AD9858 is a direct digital synthesizer (DDS) featuring a
10-bit DAC operating up to 1GSPS. The AD9858 uses advanced
DDS technology, coupled with an internal high speed, high
performance D/A converter to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sine wave at up to 400+ MHz.
The AD9858 is designed to provide fast frequency hopping and
fine tuning resolution (32-bit frequency tuning word). The
frequency tuning and control words are loaded into the AD9858
via parallel (8-bit) or serial loading formats. The AD9858
contains an integrated charge pump (CP) and phase frequency
detector (PFD) for synthesis applications requiring the
combination of a high speed DDS along with phase-locked loop
(PLL) functions. An analog mixer is also provided on-chip for
applications requiring the combination of a DDS, PLL, and
mixer, such as frequency translation loops, tuners, and so on.
The AD9858 also features a divide-by-2 on the clock input,
allowing the external clock to be as high as 2 GHz.
Up to 2 GHz input clock (selectable divide-by-2)
Integrated 10-bit D/A converter
Phase noise < 145 dBc/Hz @ 1 kHz offset
Output frequency = 100 MHz (DAC output)
32-bit programmable frequency register
Simplified 8-bit parallel and SPI® serial control interface
Automatic frequency sweeping capability
4 frequency profiles
3.3 V power supply
Power dissipation 2 W typical
Integrated programmable charge pump and phase
frequency detector with fast lock circuit
Isolated charge pump supply up to 5 V
Integrated 2 GHz mixer
APPLICATIONS
VHF/UHF LO synthesis
Tuners
The AD9858 is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
Instrumentation
Agile clock synthesis
Cellular base station hopping synthesizer
Radar
Sonet/SDH clock synthesis
FUNCTIONAL BLOCK DIAGRAM
LO
IF
RF
DIV
÷ M
PHASE
DETECTOR
PD
÷ N
AD9858
CHARGE
PUMP
ANALOG
MULTIPLIER
CP
DIGITAL PLL
CPISET
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
DACISET
PHASE-TO-
AMPLITUDE
CONVERSION
I
32
15
15
10
OUT
DAC
I
OUT
14
DAC CLOCK
32
32
TIMING AND CONTROL LOGIC
RESET
FUD
SYNCLK
CONTROL REGISTERS
POWER-
DOWN
LOGIC
÷ 8
REFCLK
REFCLK
M
U
X
÷ 2
PROFILE I/O PORT
SELECT (SER/PAR)
Figure 1.
Rev. A
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