CMOS 300 MSPS Quadrature
Complete DDS
AD9854
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interfaces
10 MHz serial 2- or 3-wire SPI compatible
100 MHz parallel 8-bit programming
3.3 V single supply
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit digital-to-analog converters (DACs)
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz ( 1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and
on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via input/output interface
Linear or nonlinear FM chirp functions with single-pin
frequency hold function
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile, quadrature LO frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciters
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode
FUNCTIONAL BLOCK DIAGRAM
DIGITAL MULTIPLIERS
SYSTEM CLOCK
INV
DDS CORE
12
SINC
4× TO 20×
REF
12
12-BIT
I
DAC
ANALOG
OUT
FILTER
REFERENCE
CLOCK IN
I
REF CLK
CLK
MULTIPLIER
BUFFER
48
48
17
17
SYSTEM
CLOCK
DAC R
SET
DIFF/SINGLE
SELECT
MUX
INV
12-BIT
Q DAC OR
CONTROL
DAC
SYSTEM
CLOCK
12
SINC
12
ANALOG
OUT
14
FILTER
48
Q
3
FSK/BPSK/HOLD
DATA IN
MUX
12
MUX
48
MUX
12
ANALOG
IN
DELTA
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
FREQUENCY
RATE TIMER
SYSTEM
CLOCK
2
48
48
14
FIRST 14-BIT
COMPARATOR
12
SYSTEM
CLOCK
12
14
CLOCK
OUT
DELTA
FREQUENCY FREQUENCY
SECOND 14-BIT
I AND Q 12-BIT
12-BIT DC
FREQUENCY
WORD
TUNING
WORD 1
TUNING
WORD 2
PHASE/OFFSET PHASE/OFFSET AM MODULATION CONTROL
WORD
WORD
PROGRAMMING REGISTERS
SYSTEM
MODE SELECT
OSK
GND
SYSTEM
CLOCK
CK
D
AD9854
BUS
÷2
INTERNAL
Q
CLOCK
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
INT
EXT
I/O PORT BUFFERS
PROGRAMMABLE
UPDATE CLOCK
+V
S
READ
WRITE SERIAL/
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
PARALLEL
SELECT
Figure 1.
Rev. E
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