Data Sheet
AD9633
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1.
AD9633-80
Temp Min Typ Max Min Typ
12 12
AD9633-105
Max Min Typ
12
AD9633-125
Parameter1
Max Unit
RESOLUTION
Bits
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Full
Full
Full
Full
Full
Full
25°C
Full
25°C
Guaranteed
Guaranteed
Guaranteed
−0.7 −0.3
−0.6 +0.2
+0.1
+0.6
0
−0.7 −0.3
−0.6 +0.2
+0.1
+0.6
0
−0.7 −0.3
−0.6 +0.2
+0.1 % FSR
+0.6 % FSR
−10
−0.6
−1.4
−5
1
−10
−0.6
−1.4
−5
1
−10
−0.6
−1.4
−5
1
0
1.5
% FSR
% FSR
1.5
1.8
+0.6
+0.6
+0.6 LSB
LSB
0.3
0.3
0.3
Integral Nonlinearity (INL)
+1.6
1.02
+1.6
1.02
+1.6 LSB
LSB
0.5
2
0.5
2
0.5
2
TEMPERATURE DRIFT
Offset Error
Full
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
Full
Full
Full
0.98 1.0
0.98 1.0
0.98 1.0
1.02
V
mV
kΩ
2
7.5
2
7.5
2
7.5
INPUT-REFERRED NOISE
VREF = 1.0 V
25°C
0.25
0.25
0.25
LSB rms
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
Full
Full
2
2
2
V p-p
V
kΩ
pF
0.9
5.2
3.5
0.9
5.2
3.5
0.9
5.2
3.5
Full
AVDD
Full
Full
Full
Full
25°C
1.7
1.7
1.8
1.8
125
59
1.9
1.9
136
80
1.7
1.7
1.8
1.8
151
63
1.9
1.9
166
97
1.7
1.7
1.8
1.8
173
66
1.9
1.9
191
101
V
V
mA
mA
mA
DRVDD
2
IAVDD
IDRVDD (ANSI-644 Mode)2
IDRVDD (Reduced Range Mode)2
TOTAL POWER CONSUMPTION
DC Input
40
43
46
Full
313
331
360
385
400
430
mW
mW
Sine Wave Input (Four Channels Including Full
Output Drivers ANSI-644 Mode)
389
473
526
Sine Wave Input (Four Channels Including 25°C
Output Drivers Reduced Range Mode)
297
349
394
mW
Power-Down
Standby3
Full
Full
2
174
2
202
2
226
mW
mW
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured with a low input frequency, full-scale sine wave on all four channels.
3 Can be controlled via the SPI.
Rev. 0 | Page 3 of 40