Datasheet > AD9633BCPZ-80

AD9633BCPZ-80

更新时间： 2024-02-04 17:41:07

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
40页	1090K
描述
Quad, 12-Bit, 80 MSPS/105 MSPS

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替代型号

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AD9633BCPZ-80 数据手册

Data Sheet

AD9633

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 3.

Parameter¹

Temp

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage²

Input Voltage Range

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

25°C

0.2

AGND − 0.2

3.6

AVDD + 0.2

V p-p

kΩ

0.9

LOGIC INPUTS (PDWN, SYNC, SCLK)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

AVDD + 0.2

0.8

Input Resistance

Input Capacitance

25°C

kΩ

LOGIC INPUT (CSB)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

AVDD + 0.2

0.8

Input Resistance

Input Capacitance

25°C

kΩ

LOGIC INPUT (SDIO)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

AVDD + 0.2

0.8

Input Resistance

Input Capacitance

25°C

kΩ

LOGIC OUTPUT (SDIO)³

Logic 1 Voltage (I_OH= 800 μA)

Logic 0 Voltage (I_OL= 50 μA)

DIGITAL OUTPUTS (D0 x, D1 x), ANSI-644

Logic Compliance

Full

1.79

0.05

LVDS

Differential Output Voltage (V_OD

)

Full

290

1.15

345

1.25

400

1.35

Output Offset Voltage (V_OS

)

Output Coding (Default)

Twos complement

DIGITAL OUTPUTS (D0 x, D1 x), LOW POWER,

REDUCED SIGNAL OPTION

Logic Compliance

LVDS

Differential Output Voltage (V_OD

)

Full

160

1.15

200

1.25

230

1.35

Output Offset Voltage (V_OS

)

Output Coding (Default)

Twos complement

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

²This is specified for LVDS and LVPECL only.

³This is specified for 13 SDIO/OLM pins sharing the same connection.

Rev. 0 | Page 5 of 40

1 2 3 456 7 8...40

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AD9633BCPZ-80 替代型号

型号	品牌	替代类型	描述	数据表
AD9633BCPZRL7-80	ADI	完全替代	Quad, 12-Bit, 80 MSPS/105 MSPS

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