Datasheet > AD9633BCPZ-80

AD9633BCPZ-80

更新时间： 2024-02-20 05:19:17

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
40页	1090K
描述
Quad, 12-Bit, 80 MSPS/105 MSPS

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数据手册
替代型号

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AD9633BCPZ-80 数据手册

AD9633

Data Sheet

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter^{1, 2}

CLOCK³

Temp

Min

Typ

Max

Unit

Input Clock Rate

Conversion Rate

Full

1000

80/105/125

MHz

MSPS

Clock Pulse Width High (t_EH)

Clock Pulse Width Low (t_EL)

OUTPUT PARAMETERS³

Propagation Delay (t_PD)

Rise Time (t_R) (20% to 80%)

Fall Time (t_F) (20% to 80%)

FCO Propagation Delay (t_FCO

DCO Propagation Delay (t_CPD

DCO to Data Delay (t_DATA

DCO to FCO Delay (t_FRAME

6.25/4.76/4.00

Full

2.3

300

2.3

)

1.5

3.1

t_FCO+ (t_SAMPLE/12)

(t_SAMPLE/12)

)

(t_SAMPLE/12) − 300

(t_SAMPLE/12) + 300

)

Lane Delay (t_LD)

Data to Data Skew (t_DATA-MAX− t_DATA-MIN

Wake-Up Time (Standby)

Wake-Up Time (Power-Down)⁵

Pipeline Latency

)

Full

200

μs

25°C

Full

250

375

Clock cycles

APERTURE

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

Out-of-Range Recovery Time

25°C

135

fs rms

Clock cycles

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

²Measured on standard FR-4 material.

³Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.

⁴t_SAMPLE/12 is based on the number of bits in two LVDS data lanes. t_SAMPLE= 1/f_S.

⁵Wake-up time is defined as the time required to return to normal operation from power-down mode.

Rev. 0 | Page 6 of 40

1...3 4 567 8 9...40

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AD9633BCPZ-80 替代型号

型号	品牌	替代类型	描述	数据表
AD9633BCPZRL7-80	ADI	完全替代	Quad, 12-Bit, 80 MSPS/105 MSPS

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AD9634BCPZ-210	ADI	获取价格	12-Bit, 170 MSPS/210 MSPS/250 MSPS
AD9634BCPZ-250	ADI	获取价格	12-Bit, 170 MSPS/210 MSPS/250 MSPS