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AD9637BCPZRL7-80 PDF预览

AD9637BCPZRL7-80

更新时间： 2024-02-04 09:31:34
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
40页 1081K
描述
Octal, 12-Bit, 40/80 MSPS, Serial LVDS

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AD9637BCPZRL7-80 技术参数

Source Url Status Check Date：2013-05-01 14:56:31.398是否无铅： 含铅
是否Rohs认证： 符合生命周期：Active
零件包装代码：QFN包装说明：HVQCCN, LCC64,.35SQ,20
针数：64Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.71最大模拟输入电压：2 V
最小模拟输入电压：-2 V最长转换时间：0.0125 µs
转换器类型：ADC, FLASH METHODJESD-30 代码：S-XQCC-N64
JESD-609代码：e3长度：9 mm
最大线性误差 (EL)：0.0293%湿度敏感等级：3
模拟输入通道数量：8位数：12
功能数量：1端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式：SERIAL
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC64,.35SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：1.8 V认证状态：Not Qualified
采样速率：80 MHz采样并保持/跟踪并保持：SAMPLE
座面最大高度：1 mm子类别：Analog to Digital Converters
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：9 mm
Base Number Matches：1

AD9637BCPZRL7-80 数据手册

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Octal, 12-Bit, 40/80 MSPS, Serial LVDS,  
1.8 V Analog-to-Digital Converter  
Data Sheet  
AD9637  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
AVDD  
PDWN  
ADC  
ADC  
ADC  
ADC  
ADC  
ADC  
ADC  
ADC  
DRVDD  
Low power: 60 mW per channel at 80 MSPS with scalable  
power options  
SNR = 71.5 dBFS (to Nyquist)  
SFDR = 92 dBc (to Nyquist)  
DNL = 0.4 LSB (typical), INL = 0.5 LSB (typical)  
Serial LVDS (ANSI-644, default)  
Low power, reduced signal option (similar to IEEE 1596.3)  
Data and frame clock outputs  
650 MHz full power analog bandwidth  
2 V p-p differential input voltage range  
1.8 V supply operation  
Serial port control  
Full chip and individual channel power-down modes  
Flexible bit orientation  
AD9637  
12  
12  
12  
12  
12  
12  
12  
12  
D+ A  
D– A  
VIN+ A  
VIN– A  
SERIAL  
LVDS  
D+ B  
D– B  
VIN+ B  
VIN– B  
SERIAL  
LVDS  
D+ C  
D– C  
VIN+ C  
VIN– C  
SERIAL  
LVDS  
D+ D  
D– D  
VIN+ D  
VIN– D  
SERIAL  
LVDS  
D+ E  
D– E  
VIN+ E  
VIN– E  
SERIAL  
LVDS  
D+ F  
D– F  
VIN+ F  
VIN– F  
SERIAL  
LVDS  
Built-in and custom digital test pattern generation  
Programmable clock and data alignment  
Programmable output resolution  
Standby mode  
D+ G  
D– G  
VIN+ G  
VIN– G  
SERIAL  
LVDS  
D+ H  
D– H  
VIN+ H  
VIN– H  
SERIAL  
LVDS  
APPLICATIONS  
VREF  
FCO+  
FCO–  
SENSE  
1.0V  
Medical imaging and nondestructive ultrasound  
Portable ultrasound and digital beam-forming systems  
Quadrature radio receivers  
DATA  
RATE  
MULTIPLIER  
VCM  
REF  
SELECT  
SERIAL PORT  
INTERFACE  
DCO+  
DCO–  
SYNC  
Diversity radio receivers  
RBIAS  
AGND  
CSB SDIO/ SCLK/  
CLK+ CLK–  
Optical networking  
DFS  
DTP  
Test equipment  
Figure 1.  
GENERAL DESCRIPTION  
clock and data alignment and programmable digital test pattern  
generation. The available digital test patterns include built-in  
deterministic and pseudorandom patterns, along with custom user-  
defined test patterns entered via the serial port interface (SPI).  
The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital  
converter (ADC) with an on-chip sample-and-hold circuit  
designed for low cost, low power, small size, and ease of use.  
The product operates at a conversion rate of up to 80 MSPS and  
is optimized for outstanding dynamic performance and low  
power in applications where a small package size is critical.  
The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is  
specified over the industrial temperature range of −40°C to +85°C.  
This product is protected by a U.S. patent.  
The ADC requires a single 1.8 V power supply and LVPECL-/  
CMOS-/LVDS-compatible sample rate clock for full performance  
operation. No external reference or driver components are  
required for many applications.  
PRODUCT HIGHLIGHTS  
1. Small Footprint. Eight ADCs are contained in a small,  
space-saving package.  
The ADC automatically multiplies the sample rate clock for the  
appropriate LVDS serial data rate. A data clock output (DCO) for  
capturing data on the output and a frame clock output (FCO) for  
signaling a new output byte are provided. Individual channel  
power-down is supported and typically consumes less than 2 mW  
when all channels are disabled.  
2. Low Power of 60 mW/Channel at 80 MSPS with Scalable  
Power Options.  
3. Ease of Use. A data clock output (DCO) is provided that  
operates at frequencies of up to 480 MHz and supports  
double data rate (DDR) operation.  
4. User Flexibility. The SPI control offers a wide range of  
flexible features to meet specific system requirements.  
5. Pin Compatible with the AD9257 (14-Bit Octal ADC).  
The ADC contains several features designed to maximize  
flexibility and minimize system cost, such as programmable  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2011 Analog Devices, Inc. All rights reserved.  
 
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