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AD9524

更新时间: 2024-02-24 15:12:11
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
56页 863K
描述
Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

AD9524 技术参数

Source Url Status Check Date:2013-05-01 14:56:31.078是否无铅: 含铅
是否Rohs认证: 符合生命周期:Not Recommended
包装说明:HVQCCN,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.26
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:7 mm端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:1000 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE主时钟/晶体标称频率:250 MHz
座面最大高度:1 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:7 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

AD9524 数据手册

 浏览型号AD9524的Datasheet PDF文件第6页浏览型号AD9524的Datasheet PDF文件第7页浏览型号AD9524的Datasheet PDF文件第8页浏览型号AD9524的Datasheet PDF文件第10页浏览型号AD9524的Datasheet PDF文件第11页浏览型号AD9524的Datasheet PDF文件第12页 
Data Sheet  
AD9524  
TIMING ALIGNMENT CHARACTERISTICS  
Table 10.  
Parameter  
Min Typ Max Unit  
Test Conditions/Comments  
OUTPUT TIMING SKEW  
Delay off on all outputs; maximum deviation  
between rising edges of outputs; all outputs are on,  
unless otherwise noted.  
Between LVPECL, HSTL, and LVDS Outputs  
Between CMOS Outputs  
Adjustable Delay  
38  
234  
ps  
ps  
100 300  
63  
Single-ended true phase high-Z mode  
0
Steps Resolution step; for example, 8 × 0.5/1 GHz  
Resolution Step  
Zero Delay  
Between Input Clock Edge on REFA or  
REFB to ZD_IN Input Clock Edge,  
External Zero Delay Mode  
500  
ps  
ps  
½ period of 1 GHz  
150 500  
PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 μA, RZERO = 10 kΩ,  
antibacklash pulse width is at maximum, BW = 40 Hz,  
REFA and ZD_IN are set to differential mode  
JITTER AND NOISE CHARACTERISTICS  
Table 11.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
OUTPUT ABSOLUTE RMS TIME JITTER  
Application example based on a typical setup  
(see Table 3); f = 122.88 MHz  
LVPECL Mode, HSTL Mode, LVDS Mode  
125  
136  
169  
212  
223  
fs  
fs  
fs  
fs  
fs  
Integrated BW = 200 kHz to 5 MHz  
Integrated BW = 200 kHz to 10 MHz  
Integrated BW = 12 kHz to 20 MHz  
Integrated BW = 10 kHz to 61 MHz  
Integrated BW = 1 kHz to 61 MHz  
PLL2 CHARACTERISTICS  
Table 12.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
VCO (ON CHIP)  
Frequency Range  
Gain  
3600  
4000  
MHz  
MHz/V  
dBc/Hz  
45  
PLL2 FIGURE OF MERIT (FOM)  
MAXIMUM PFD FREQUENCY  
Antibacklash Pulse Width  
Minimum and Low  
Maximum and High  
−226  
250  
125  
MHz  
MHz  
Rev. D | Page 9 of 56  
 
 
 
 

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