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AD9524

更新时间： 2024-01-09 20:18:42
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
56页 863K
描述
Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

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AD9524 技术参数

Source Url Status Check Date：2013-05-01 14:56:31.078是否无铅： 含铅
是否Rohs认证： 符合生命周期：Not Recommended
包装说明：HVQCCN,针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.26
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：7 mm端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：1000 MHz封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE主时钟/晶体标称频率：250 MHz
座面最大高度：1 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：7 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

AD9524 数据手册

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AD9524  
Data Sheet  
POWER DISSIPATION  
Table 3.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
POWER DISSIPATION  
Typical Configuration  
559  
593  
mW  
Clock distribution outputs running as follows: four LVPECL outputs  
at 122.88 MHz, two LVDS outputs (3.5 mA) at 122.88 MHz,  
one differential input reference at 30.72 MHz; fVCXO = 122.88 MHz,  
fVCO = 3932.16 MHz; PLL2 BW = 530 kHz; doubler is off  
PD, Power-Down  
101  
389  
132.2  
450.4  
mW  
mW  
PD pin pulled low, with typical configuration conditions  
INCREMENTAL POWER DISSIPATION  
Low Power Typical Configuration  
Absolute total power with clock distribution; one LVPECL output  
running at 122.88 MHz; one differential input reference at  
30.72 MHz; fVCXO = 122.88 MHz, fVCO = 3932.16 MHz; doubler is off  
Switched to One Input,  
Reference Single-Ended Mode  
Switched to Two Inputs,  
Reference Differential Mode  
−28.5  
26  
−8  
mW  
mW  
mW  
Running at 30.72 MHz  
Running at 30.72 MHz  
Running at 30.72 MHz  
44.6  
−5.1  
Switched to Two Inputs,  
−27.5  
Reference Single-Ended Mode  
Output Distribution, Driver On  
LVDS  
Incremental power increase (OUT1) from low power typical (3.3 V)  
Single 3.5 mA LVDS output at 245.76 MHz  
Single 7 mA LVDS output at 61.44 MHz  
15.3  
47.8  
50.1  
40.2  
43.7  
6.6  
18.4  
55.4  
54.9  
46.3  
50.3  
7.9  
mW  
mW  
mW  
mW  
mW  
mW  
mW  
mW  
LVPECL Compatible  
HSTL  
Single LVPECL output at 122.88 MHz  
Single 8 mA HSTL output at 122.88 MHz  
Single 16 mA HSTL output at 122.88 MHz  
Single 3.3 V CMOS output at 15.36 MHz  
Dual complementary 3.3 V CMOS output at 15.36 MHz  
Dual in-phase 3.3 V CMOS output at 15.36 MHz  
CMOS  
9.9  
9.9  
11.9  
11.9  
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS  
Table 4.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DIFFERENTIAL MODE  
Input Frequency Range  
Input Slew Rate (OSC_IN)  
Common-Mode Internally  
Generated Input Voltage  
Input Common-Mode Range  
Differential Input Voltage,  
Sensitivity Frequency < 250 MHz  
400  
MHz  
V/µs  
V
400  
0.6  
Minimum limit imposed for jitter performance  
For dc-coupled LVDS (maximum swing)  
0.7  
0.8  
1.025  
100  
1.475  
V
mV p-p Capacitive coupling required; can accommodate single-ended  
input by ac grounding of unused input; the instantaneous voltage  
on either pin must not exceed the 1.8 V dc supply rails  
Differential Input Voltage,  
Sensitivity Frequency > 250 MHz  
200  
mV p-p Capacitive coupling required; can accommodate single-ended  
input by ac grounding of unused input; the instantaneous voltage  
on either pin must not exceed the 1.8 V dc supply rails  
Differential Input Resistance  
Differential Input Capacitance  
Duty Cycle  
4.8  
1
kΩ  
pF  
Duty cycle bounds are set by pulse width high and pulse width low  
Pulse Width Low  
Pulse Width High  
1
1
ns  
ns  
CMOS MODE SINGLE-ENDED INPUT  
Input Frequency Range  
Input High Voltage  
250  
MHz  
V
1.6  
Input Low Voltage  
0.52  
V
Input Threshold Voltage  
1.0  
V
When ac coupling to the input receiver, the user must dc bias the  
input to 1 V; the single-ended CMOS input is 3.3 V compatible  
Rev. D | Page 6 of 56  
 
 
 
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