Quad Input, 10-Output, Dual DPLL/IEEE 1588
Synchronizer and Jitter Cleaner
Data Sheet
AD9543
FEATURES
APPLICATIONS
Dual DPLL synchronizes 2 kHz to 750 MHz physical layer
clocks providing frequency translation with jitter cleaning
of noisy references
PTP (IEEE 1588), and SyncE jitter cleanup and
synchronization
Optical transport networks (OTN), SDH, and macro and small
cell base stations
Complies with ITU-T G.8262 and Telcordia GR-253
Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823,
G.824, G.825, and G.8273.2
OTN mapping/demapping with jitter cleaning
Small base station clocking, including baseband and radio
Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter
cleanup, and phase transient control
JESD204B support for analog-to-digital converter (ADC) and
digital-to-analog converter (DAC) clocking
Cable infrastructures
Continuous frequency monitoring and reference validation
for frequency deviation as low as 50 ppb
Both DPLLs feature a 24-bit fractional divider with 24-bit
programmable modulus
Programmable digital loop filter bandwidth: 10−4 Hz to 1850 Hz
Two independent, programmable auxiliary NCOs (1 Hz to
65,535 Hz, resolution < 1.4 × 10−12 Hz), suitable for
IEEE 1588 Version 2 servo feedback in PTP applications
Automatic and manual holdover and reference switchover,
providing zero delay, hitless, or phase buildout operation
Programmable priority-based reference switching with
manual, automatic revertive, and automatic nonrevertive
modes supported
Carrier Ethernet
GENERAL DESCRIPTION
The AD9543 supports existing and emerging ITU standards for
the delivery of frequency, phase, and time of day over service
provider packet networks.
The 10 clock outputs of the AD9543 are synchronized to any
one of up to four input references. The digital phase-locked
loops (DPLLs) reduce timing jitter associated with the external
references. The digitally controlled loop and holdover circuitry
continuously generate a low jitter output signal, even when all
reference inputs fail.
5 pairs of clock output pins with each pair useable as
differential LVDS/HCSL/CML or as 2 single-ended outputs
(1 Hz to 500 MHz)
2 differential or 4 single-ended input references
Crosspoint mux interconnects reference inputs to PLLs
Supports embedded (modulated) input/output clock signals
Fast DPLL locking modes
The AD9543 is available in a 48-lead LFCSP (7 mm × 7 mm)
package and operates over the −40°C to +85°C temperature
range.
Provides internal capability to combine the low phase noise
of a crystal resonator or crystal oscillator with the
frequency stability and accuracy of a TCXO or OCXO
External EEPROM support for autonomous initialization
Single 1.8 V power supply operation with internal regulation
Built in temperature monitor/alarm and temperature
compensation for enhanced zero delay performance
Note that throughout this data sheet, multifunction pins, such
as SDO/M5, are referred to either by the entire pin name or by a
single function of the pin, for example, M5, when only that
function is relevant.
Rev. 0
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