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AD9524

更新时间： 2024-01-30 17:14:43
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
56页 863K
描述
Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

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AD9524 技术参数

Source Url Status Check Date：2013-05-01 14:56:31.078是否无铅： 含铅
是否Rohs认证： 符合生命周期：Not Recommended
包装说明：HVQCCN,针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.26
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：7 mm端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：1000 MHz封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE主时钟/晶体标称频率：250 MHz
座面最大高度：1 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：7 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

AD9524 数据手册

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AD9524  
Data Sheet  
SPECIFICATIONS  
fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 3932.16 MHz, doubler is off, channel control  
low power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V 5%, and TA = 25°C, unless otherwise  
noted. Minimum and maximum values are given over the full VDD and TA (−40°C to +85°C) variation, as listed in Table 1.  
CONDITIONS  
Table 1.  
Parameter  
Min Typ Max  
Unit  
Test Conditions/Comments  
SUPPLY VOLTAGE  
VDD3_PLL1, Supply Voltage for PLL1  
VDD3_PLL2, Supply Voltage for PLL2  
VDD3_REF, Supply Voltage Clock Output Drivers Reference  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers  
TEMPERATURE  
3.3  
3.3  
3.3  
3.3  
1.8  
V
V
V
V
V
3.3 V 5%  
3.3 V 5%  
3.3 V 5%  
3.3 V 5%  
1.8 V 5%  
Ambient Temperature Range, TA  
Junction Temperature, TJ  
−40 +25 +85  
115  
°C  
°C  
1
OUT0  
x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0,  
(Pin 41 and Pin 40,  
OUT1  
respectively) and Supply Voltage Clock Output OUT1,  
(Pin 38 and Pin 37, respectively).  
SUPPLY CURRENT  
Table 2.  
Parameter  
Min Typ  
Max  
Unit Test Conditions/Comments  
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS  
VDD3_PLL1, Supply Voltage for PLL1  
37  
67  
43  
mA  
mA  
Decreases by 9 mA typical if REFB is turned  
off  
VDD3_PLL2, Supply Voltage for PLL2  
77.7  
VDD3_REF, Supply Voltage Clock Output Drivers  
Reference  
LVPECL Mode  
5
4
6
mA  
mA  
Only one output driver turned on; for each  
additional output that is turned on, the current  
increments by 1.2 mA maximum  
Only one output driver turned on; for each  
additional output that is turned on, the current  
increments by 1.2 mA maximum  
LVDS Mode  
4.8  
HSTL Mode  
CMOS Mode  
3
3
3.6  
3.6  
4.2  
mA  
mA  
mA  
Values are independent of the number of  
outputs turned on  
Values are independent of the number of  
outputs turned on  
Current for each divider: f = 245.76 MHz  
Channel x control register, Bit 4 = 0  
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers2  
CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF  
LVDS Mode, 7 mA  
3.5  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
LVDS Mode, 3.5 mA  
11.5  
40  
13.2  
45  
mA  
mA  
f = 122.88 MHz  
f = 983.04 MHz  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
LVPECL Compatible Mode  
6.5  
23  
7.5  
26.3  
mA  
mA  
f = 122.88 MHz  
f = 983.04 MHz  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
HSTL Mode, 8 mA  
13  
41  
14.4  
46.5  
mA  
mA  
f = 122.88 MHz  
f = 983.04 MHz  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
CMOS Mode (Single-Ended)  
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers  
14  
16.3  
2.4  
mA  
mA  
f = 122.88 MHz  
2
f = 15.36 MHz, 10 pF load  
Rev. D | Page 4 of 56  
 
 
 
 
 
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