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AD9540PCB PDF预览

AD9540PCB

更新时间: 2024-01-25 07:23:34
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
32页 483K
描述
655 MHz Low Jitter Clock Generator

AD9540PCB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:48
Reach Compliance Code:unknown风险等级:5.83
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:7 mm湿度敏感等级:3
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
主时钟/晶体标称频率:2700 MHz认证状态:COMMERCIAL
座面最大高度:1 mm最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:7 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER

AD9540PCB 数据手册

 浏览型号AD9540PCB的Datasheet PDF文件第2页浏览型号AD9540PCB的Datasheet PDF文件第3页浏览型号AD9540PCB的Datasheet PDF文件第4页浏览型号AD9540PCB的Datasheet PDF文件第5页浏览型号AD9540PCB的Datasheet PDF文件第6页浏览型号AD9540PCB的Datasheet PDF文件第7页 
655 MHz Low Jitter Clock Generator  
AD9540  
FEATURES  
APPLICATIONS  
Excellent intrinsic jitter performance  
25 Mb/s write-speed serial I/O control  
200 MHz phase frequency detector inputs  
Clocking high performance data converters  
Base station clocking applications  
Network (SONET/SDH) clocking  
655 MHz programmable input dividers for the phase fre-  
quency detector (÷M, ÷N) {M, N = 1..16} (bypassable)  
Gigabit Ethernet (GbE) clocking  
Instrumentation clocking circuits  
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)  
8 programmable internal clock rates  
Programmable edge delay with 93 fS resolution  
1.8 V supply for device operation  
3.3 V supply for I/O, CML driver, and charge pump output  
Software controlled power-down  
48-lead LFCSP package  
Programmable charge pump current (up to 4 mA)  
Multichip synchronization  
Dual-mode PLL lock detect  
655 MHz CML-mode PECL-compliant driver  
FUNCTIONAL BLOCK DIAGRAM  
AVDD AGND DVDD DGND VCML VCP  
CP_RSET  
CP  
REF, AMP  
REFIN  
REFIN  
M DIVIDER  
N DIVIDER  
PHASE  
FREQUENCY  
DETECTOR  
CHARGE  
PUMP  
CP  
CLK2  
CLK2  
SYNC, PLL  
LOCK  
SYNC_IN/STATUS  
CLK1  
CLK1  
DRV_RSET  
OUT0  
CML  
DIVIDER  
1, 2, 4, 8  
OUT0  
VCML  
SCLK  
SDI/O  
SDO  
CS  
SERIAL  
CONTROL  
PORT  
CLK  
TIMING AND  
CONTROL LOGIC  
DIVCLK  
48  
14  
S2  
S1  
S0  
PHASE/  
FREQUENCY  
PROFILES  
IOUT  
IOUT  
10  
DDS  
DAC  
DAC_RSET  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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