16-Bit, 80/100 MSPS ADC
AD9446
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD
DFS
100 MSPS guaranteed sampling rate (AD9446-100)
83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS)
82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS)
89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS)
95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = 0.4 LSB typical
INL = 3.0 LSB typical
AD9446
DCS MODE
OUTPUT MODE
OR
BUFFER
16
VIN+
VIN–
2
PIPELINE
ADC
CMOS
OR
LVDS
T/H
32
D15 TO D0
DCO
OUTPUT
STAGING
2
CLOCK
AND TIMING
MANAGEMENT
CLK+
CLK–
REF
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
VREF SENSE REFT REFB
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
Figure 1.
3.3 V and 5 V supply operation
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
APPLICATIONS
MRI receivers
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
The AD9446 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP/EP) specified over the
industrial temperature range −40°C to +85°C.
Radar
Infrared imaging
PRODUCT HIGHLIGHTS
Communications instrumentation
1. True 16-bit linearity.
2. High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
GENERAL DESCRIPTION
The AD9446 is a 16-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
product operates up to a 100 MSPS, providing superior SNR for
instrumentation, medical imaging, and radar receivers
employing baseband (<100 MHz) IF frequencies.
3. Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
4. Packaged in a Pb-free, 100-lead TQFP/EP package.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.
5. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6. OR (out-of-range) outputs indicate when the signal is
beyond the selected input range.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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