16-Bit, 80 MSPS/105 MSPS ADC
AD9460
FEATURES
FUNCTIONAL BLOCK DIAGRAM
105 MSPS guaranteed sampling rate (AD9460-105)
AGND AVDD1 AVDD2 DRGND DRVDD
79.4 dBFS SNR/91 dBc SFDR with 10 MHz input
(3.4 V p-p input, 80 MSPS)
DFS
AD9460
DCS MODE
BUFFER
78.3 dBFS SNR/ with 170 MHz input
(4.0 V p-p input, 80 MSPS)
77.8 dBFS SNR/87 dBc SFDR with 170 MHz input
(3.4 V p-p input, 80 MSPS)
OUTPUT MODE
16
VIN+
VIN–
2
PIPELINE
ADC
T/H
CMOS
OR
OR
32
LVDS
OUTPUT
STAGING
D15 TO D0
2
77.2 dBFS SNR/84 dBc SFDR with 170 MHz input
(3.4 V p-p input, 105 MSPS)
CLK+
CLK–
CLOCK
DCO
AND TIMING
REF
MANAGEMENT
90 dBFS two-tone SFDR with 139 MHz/140 MHz input
(3.4 V p-p input, 105 MSPS)
VREF SENSE REFT REFB
60 fsec rms jitter
Excellent linearity
Figure 1.
DNL = 0.5 LSB typical
INL = 3.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output data capture clock available
3.3 V and 5 V supply operation
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
APPLICATIONS
MRI receivers
Multicarrier, multimode, cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
The AD9460 is available in a Pb-free, 100-lead, surface-mount,
plastic package (TQFP_EP) specified over the industrial tem-
perature range of −40°C to +85°C.
Radar
PRODUCT HIGHLIGHTS
Infrared imaging
Communications instrumentation
1. True 16-bit linearity.
GENERAL DESCRIPTION
2. High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
AD9460 operates up to 105 MSPS, providing a superior signal-
to-noise ratio (SNR) for instrumentation, medical imaging, and
radar receivers using baseband (<100 MHz) and IF frequencies.
3. Ease of use: on-chip reference and high input impedance,
track-and-hold with adjustable analog input range, and an
output clock simplifies data capture.
4. Packaged in a Pb-free, 100-lead TQFP/EP.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS compatible
(ANSI-644 compatible) and include the means to reduce the
overall current needed for short trace distances.
5. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6. Out-of-range (OR) outputs indicate when the signal is
beyond the selected input range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
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