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AD9289-65EB

更新时间: 2024-10-29 01:22:59
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亚德诺 - ADI /
页数 文件大小 规格书
33页 917K
描述
Serial LVDS 3 V A/D Converter

AD9289-65EB 数据手册

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Quad 8-Bit, 65 MSPS,  
Serial LVDS 3 V A/D Converter  
AD9289  
FEATURES  
Four ADCs in one package  
FUNCTIONAL BLOCK DIAGRAM  
AVDD  
DFS  
PDWN  
DTP  
DRVDD  
DRGND  
Serial LVDS digital output data rates to 520 Mbps (ANSI-644)  
Data and frame clock outputs  
SNR = 48 dBc (to Nyquist)  
AD9289  
VIN+A  
VIN–A  
8
D1+A  
D1–A  
SERIAL  
LVDS  
PIPELINE  
ADC  
SHA  
Excellent linearity  
DNL = 0.2 LSB (typical)  
INL = 0.25 LSB (typical)  
300 MHz full power analog bandwidth  
Power dissipation = 112 mW/channel at 65 MSPS  
1 Vp-p to 2 Vp-p input voltage range  
3.0 V supply operation  
VIN+B  
VIN–B  
8
8
8
D1+B  
D1–B  
SERIAL  
LVDS  
PIPELINE  
ADC  
SHA  
SHA  
SHA  
VIN+C  
VIN–C  
D1+C  
D1–C  
SERIAL  
LVDS  
PIPELINE  
ADC  
VIN+D  
VIN–D  
D1+D  
D1–D  
SERIAL  
LVDS  
PIPELINE  
ADC  
Power-down mode  
Digital test pattern enable for timing alignments  
LOCK  
VREF  
SENSE  
FCO+  
FCO–  
0.5V  
REFT_A  
REFB_A  
REFT_B  
REFB_B  
APPLICATIONS  
Tape drives  
Medical imaging  
REF  
SELECT  
DCO+  
DCO–  
DATA RATE  
MULTIPLIER  
SHARED_REF AGND LVDSBIAS CML CLK+ CLK–  
Figure 1.  
PRODUCT HIGHLIGHTS  
PRODUCT DESCRIPTION  
The AD9289 is a quad 8-bit, 65 MSPS analog-to-digital conver-  
ter (ADC) with an on-chip sample-and-hold circuit that is  
designed for low cost, low power, small size, and ease of use.  
The product operates at up to a 65 MSPS conversion rate and is  
optimized for outstanding dynamic performance where a small  
package size is critical.  
1. Four ADCs are contained in a small, space-saving package.  
2. A data clock out (DCO) is provided, which operates up to  
260 MHz and supports double-data rate operation (DDR).  
3. The outputs of each ADC are serialized LVDS with data  
rates up to 520 Mbps (8 bits × 65 MSPS).  
The ADC requires a single, 3 V power supply and an LVDS-  
compatible sample rate clock for full performance operation.  
No external reference or driver components are required for  
many applications.  
4. The AD9289 operates from a single 3.0 V power supply.  
5. The internal clock duty cycle stabilizer maintains  
performance over a wide range of input clock duty cycles.  
The ADC automatically multiplies the sample rate clock for the  
appropriate LVDS serial data rate. A data clock (DCO) for  
capturing data on the output and a frame clock (FCO) trigger  
for signaling a new output byte are provided. Power-down is  
supported. The ADC typically consumes 7 mW when enabled.  
Fabricated on an advanced CMOS process, the AD9289 is  
available in a 64-ball mini-BGA package (64-BGA). It is  
specified over the industrial temperature range of –40°C  
to +85°C.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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