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AD9363ABCZ-REEL

更新时间: 2024-10-29 01:12:35
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亚德诺 - ADI /
页数 文件大小 规格书
32页 523K
描述
Radio frequency (RF) 2 × 2 transceiver with integrated 12-bit DACs and ADCs

AD9363ABCZ-REEL 数据手册

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RF Agile Transceiver  
Data Sheet  
AD9363  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
RX1B_P,  
RX1B_N  
Radio frequency (RF) 2 × 2 transceiver with integrated 12-bit  
DACs and ADCs  
Wide bandwidth: 325 MHz to 3.8 GHz  
Supports time division duplex (TDD) and frequency division  
duplex (FDD) operation  
AD9363  
RX1A_P,  
RX1A_N  
ADC  
RX1C_P,  
RX1C_N  
RX2B_P,  
RX2B_N  
P0_D11/  
TX_D5_x TO P0_D0/  
TX_D0_x  
Tunable channel bandwidth (BW): up to 20 MHz  
Receivers: 6 differential or 12 single-ended inputs  
Superior receiver sensitivity with a noise figure: 3 dB  
Receive (Rx) gain control  
RX2A_P,  
RX2A_N  
ADC  
RX2C_P,  
RX2C_N  
RX LO  
TX LO  
TX_MON1  
P1_D11/  
Real-time monitor and control signals for manual gain  
Independent automatic gain control (AGC)  
Dual transmitters: 4 differential outputs  
Highly linear broadband transmitter  
Transmit (Tx) error vector magnitude (EVM): −34 dB  
Tx noise: ≤−157 dBm/Hz noise floor  
Tx monitor: 66 dB dynamic range with 1 dB accuracy  
Integrated fractional N synthesizers  
2.4 Hz local oscillator (LO) step size  
TX1A_P,  
TX1A_N  
DAC  
DAC  
RX_D5_x TO P1_D0/  
RX_D0_x  
TX1B_P,  
TX1B_N  
TX_MON2  
TX2A_P,  
TX2A_N  
TX2B_P,  
TX2B_N  
RADIO  
SWITCHING  
GPO  
SPI  
CTRL  
PLLs  
CLK_OUT  
CTRL  
AUXADC AUXDACx  
XTALN  
CMOS/LVDS digital interface  
NOTES  
1. SPI, CTRL, P0_D11/TX_D5_x TO P0_D0/TX_D0_x, P1_D11/  
RX_D5_x TO P1_D0/RX_D0_x, AND RADIO SWITCHING  
CONTAIN MULTIPLE PINS.  
APPLICATIONS  
3G enterprise femtocell base stations  
4G femtocell base stations  
Figure 1.  
Wireless video transmission  
GENERAL DESCRIPTION  
The AD9363 is a high performance, highly integrated RF agile  
transceiver designed for use in 3G and 4G femtocell applications.  
Its programmability and wideband capability make it ideal for a  
broad range of transceiver applications. The device combines an  
RF front end with a flexible mixed-signal baseband section and  
integrated frequency synthesizers, simplifying design-in by  
providing a configurable digital interface to a processor. The  
AD9363 operates in the 325 MHz to 3.8 GHz range, covering  
most licensed and unlicensed bands. Channel bandwidths from  
less than 200 kHz to 20 MHz are supported.  
sample rate.  
The transmitters use a direct conversion architecture that achieves  
high modulation accuracy with ultralow noise. This transmitter  
design produces a best-in-class Tx EVM of −34 dB, allowing  
significant system margin for the external power amplifier (PA)  
selection. The on-board Tx power monitor can be used as a  
power detector, enabling highly accurate Tx power  
measurements.  
The fully integrated phase-locked loops (PLLs) provide low  
power fractional N frequency synthesis for all receive and  
transmit channels. Channel isolation, demanded by FDD  
systems, is integrated into the design. All voltage controlled  
oscillators (VCOs) and loop filter components are integrated.  
The two independent direct conversion receivers have state-of-  
the-art noise figure and linearity. Each Rx subsystem includes  
independent automatic gain control (AGC), dc offset correction,  
quadrature correction, and digital filtering, thereby eliminating  
the need for these functions in the digital baseband. The AD9363  
also has flexible manual gain modes that can be externally  
controlled. Two high dynamic range ADCs per channel digitize  
the received I and Q signals and pass them through configurable  
decimation filters and 128-tap finite impulse response (FIR)  
filters to produce a 12-bit output signal at the appropriate  
The core of the AD9363 can be powered directly from a 1.3 V  
regulator. The IC is controlled via a standard 4-wire serial port  
and four real-time I/O control pins. Comprehensive power-down  
modes are included to minimize power consumption during  
normal use. The AD9363 is packaged in a 10 mm × 10 mm,  
144-ball chip scale package ball grid array (CSP_BGA).  
Rev. D  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2016 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 

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