Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
Serial LVDS 1.8 V Analog-to-Digital Converter
Data Sheet
AD9253
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
1.8 V supply operation
14
Low power: 110 mW per channel at 125 MSPS with scalable
power options
SNR = 74 dB (to Nyquist)
D0+A
D0–A
SERIAL
LVDS
VIN+A
VIN–A
DIGITAL
PIPELINE
ADC
SERIALIZER
D1+A
D1–A
SERIAL
LVDS
14
VIN+B
DIGITAL
SERIALIZER
PIPELINE
ADC
D0+B
D0–B
SERIAL
LVDS
SFDR = 90 dBc (to Nyquist)
VIN–B
RBIAS
VREF
DNL = 0.75 LSB (typical); INL = 2.0 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced
signal option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
SERIAL
LVDS
D1+B
D1–B
SENSE
FCO+
FCO–
D0+C
D0–C
D1+C
D1–C
1V
AD9253
REF
SELECT
SERIAL
LVDS
AGND
14
14
VIN+C
VIN–C
DIGITAL
SERIALIZER
PIPELINE
ADC
SERIAL
LVDS
D0+D
D0–D
SERIAL
LVDS
VIN+D
VIN–D
DIGITAL
SERIALIZER
PIPELINE
ADC
D1+D
D1–D
DCO+
DCO–
SERIAL
LVDS
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
VCM
APPLICATIONS
Figure 1.
Medical ultrasound
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
as programmable output clock and data alignment and digital
test pattern generation. The available digital test patterns
include built-in deterministic and pseudorandom patterns, along
with custom user-defined test patterns entered via the serial port
interface (SPI).
GENERAL DESCRIPTION
The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS
analog-to-digital converter (ADC) with an on-chip sample-
and-hold circuit designed for low cost, low power, small size,
and ease of use. The product operates at a conversion rate of
up to 125 MSPS and is optimized for outstanding dynamic
performance and low power in applications where a small
package size is critical.
The AD9253 is available in a RoHS-compliant, 48-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 110 mW/channel at 125 MSPS with scalable
power options.
3. Pin compatible to the AD9633 12-bit quad ADC.
4. Ease of Use. A data clock output (DCO) operates at
frequencies of up to 500 MHz and supports double data
rate (DDR) operation.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such
5. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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