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AD9255BCPZRL7-105 PDF预览

AD9255BCPZRL7-105

更新时间: 2024-10-28 12:32:59
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
44页 1757K
描述
14-Bit, 125 MSPS/105 MSPS/80 MSPS

AD9255BCPZRL7-105 数据手册

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14-Bit, 125 MSPS/105 MSPS/80 MSPS,  
1.8 V Analog-to-Digital Converter  
Data Sheet  
AD9255  
FEATURES  
APPLICATIONS  
SNR = 78.3 dBFS at 70 MHz and 125 MSPS  
SFDR = 93 dBc at 70 MHz and 125 MSPS  
Low power: 371 mW at 125 MSPS  
Communications  
Multimode digital receivers (3G)  
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and  
TD-SCDMA  
1.8 V analog supply operation  
1.8 V CMOS or LVDS output supply  
Smart antenna systems  
Integer 1-to-8 input clock divider  
General-purpose software radios  
Broadband data applications  
Ultrasound equipment  
IF sampling frequencies to 300 MHz  
−153.4 dBm/Hz small signal input noise with 200 Ω input  
impedance at 70 MHz and 125 MSPS  
Optional on-chip dither  
PRODUCT HIGHLIGHTS  
1. On-chip dither option for improved SFDR performance  
with low power analog input.  
2. Proprietary differential input that maintains excellent SNR  
performance for input frequencies up to 300 MHz.  
3. Operation from a single 1.8 V supply and a separate digital  
output driver supply accommodating 1.8 V CMOS or  
LVDS outputs.  
4. Standard serial port interface (SPI) that supports various  
product features and functions, such as data formatting  
(offset binary, twos complement, or gray coding), enabling  
the clock DCS, power-down, test modes, and voltage  
reference mode.  
Programmable internal ADC voltage reference  
Integrated ADC sample-and-hold inputs  
Flexible analog input range: 1 V p-p to 2 V p-p  
Differential analog inputs with 650 MHz bandwidth  
ADC clock duty cycle stabilizer  
Serial port control  
User-configurable, built-in self-test (BIST) capability  
Energy-saving power-down modes  
5. Pin compatibility with the AD9265, allowing a simple  
migration up to 16 bits.  
FUNCTIONAL BLOCK DIAGRAM  
SENSE RBIAS PDWN  
AGND AVDD (1.8V)  
LVDS LVDS_RS  
REFERENCE  
VREF  
AD9255  
VCM  
DRVDD (1.8V)  
D13 TO D0  
VIN+  
TRACK-AND-HOLD  
VIN–  
OUTPUT  
ADC  
14  
STAGING  
CMOS OR  
LVDS  
14  
14-BIT  
DITHER  
CORE  
(DDR)  
CLK+  
CLOCK  
MANAGEMENT  
OR  
CLK–  
OEB  
SYNC  
SERIAL PORT  
DCO  
SVDD SCLK/ SDIO/ CSB  
DFS DCS  
Figure 1.  
Rev. C  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

AD9255BCPZRL7-105 替代型号

型号 品牌 替代类型 描述 数据表
AD9255BCPZ-105 ADI

完全替代

14-Bit, 125 MSPS/105 MSPS/80 MSPS
AD9265BCPZ-80 ADI

类似代替

16-Bit, 125 MSPS/105 MSPS/80 MSPS 1.8 V Analog-to-Digital Converter
AD9255BCPZ-80 ADI

功能相似

14-Bit, 125 MSPS/105 MSPS/80 MSPS

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